IEEE Circuits and Systems Magazine - Q4 2022 - 43

storage layer, which shifts the threshold voltage VT of
the transistor channel. The threshold voltage in turn
modulates the cell's drain current ID. The SONOS gate
stack and write process were optimized for operation
as approximate memory [5,63]. Histograms of the cell
drain current, measured at VT = 0 V and VD = 0.1 V, are
shown in Fig. 22(a) for various target currents with Imax
= 1.6µA. The same biases are used during an MVM. Each
histogram is fit to a normal distribution whose width is
the expected programming error in a cell.
Fig. 22(b) shows the error as a function of current.
The cell error is approximately state-proportional below
0.5µA with αprop ≈ 6%, and saturates at high conductance.
This property comes from the fact that the SONOS transistor
is designed to operate in the subthreshold regime
at a fixed bias of VG = 0 V:
II0 exp K
D
§
©
¨
qV
kT
T
·
¹
¸
(10)
where I0 is a constant, η is the gate efficiency, q is the
electron charge, k is the Boltzmann constant, and T is
the temperature. Differentiating the above with respect
to VT gives:
dI
qK
DT D
kT
dV I
u
(11)
Since the amount of stored charge is related linearly to
VT, the error in the charge injection or removal process
is proportional to the error dVT. Equation (11) shows that
for the same error in the write process, the error in the
cell current dID is proportional to the cell current ID. This
is consistent with the data in Fig. 22(b). At currents above
around 0.8µA, corresponding to lower VT, the device leaves
the subthreshold regime and the error consequently
increases sublinearly with the current. As discussed in
Section 5, state-proportional error is highly advantageous
for neural network inference, as it matches the most frequently
used weight values to devices with the least error.
The state-dependent error of the SONOS device is
modeled within CrossSim using a saturating exponential
fit to the data, shown in Fig. 22(b). The SONOS cell is
used as an approximate 7-bit memory; the modeled program
error distributions of the 128 target current levels

IEEE Circuits and Systems Magazine - Q4 2022

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