IEEE Circuits and Systems Magazine - Q4 2022 - 44

Offset-subtraction cores have a more limited design
space. Fig. 17 shows that due to 8-bit ADC quantization
alone, offset subtraction can reach high accuracy only
with a small array (≤ 144 rows) and finer bit slices (≤ 2
bits/cell). Sections 5 and 8 showed that they are also
more sensitive to cell errors and parasitic resistance,
which might further reduce the array size. Additionally,
the absence of proportional mapping requires larger and
more power-hungry peripheral circuits that can support
larger bit line currents, as shown in Fig. 20. For these reasons,
only four design points are evaluated for offset subtraction,
both using digital input bit accumulation: 72 and
144 rows with 1 and 2 bits per cell, which are close to the
design point in ISAAC [56]. One of these designs is shown
in Fig. 23(b) and requires multiple digital steps to aggregate
partial results produced by the analog hardware.
All energy and area estimates are based on SONOS
arrays and peripheral circuits that are designed and
simulated with SPICE in an embedded 40nm process
compatible with SONOS memory [5], [37], [63]. The
energy consumption of the array and row drivers is
based on the average cell conductances in Fig. 7 and
the average activity factors for each input bit when running
ResNet50-v1.5 on ImageNet. The core uses a current
conveyor that integrates each input bit for 10 ns
[45], a switched-capacitor circuit for analog input bit
accumulation [8], and a power- and area-efficient 8-bit
ramp ADC clocked at 1GHz [45]. ADC range calibration is
implemented with a tunable operational-amplifier gain
stage after the integrator. Digital component energies
are derived from a standard cell library. Since all array
outputs are simultaneously available with a ramp ADC,
as many S&A units are allocated as needed to process
these results in parallel. Area is estimated from the sum
of circuit block areas rather than a physical layout.
9.3. Energy and Area Evaluation
Fig. 24(a) shows the energy efficiency of various core
configurations. To estimate the peak efficiency, a
1152 × 256 weight matrix is evaluated that utilizes every
cell in each array. Table 3 details the area and energy
efficiency of five labeled configurations in Fig. 24(a),
whose energy breakdown among core components is
shown in Fig. 24(b). These results reveal several trends:
1) Unsliced weights are more efficient than bit slicing
because the bit line peripheral circuit costs
increase roughly linearly with the number of
slices. The area increases linearly with bit slicing
due to having more cells per weight.
2) Larger arrays are more efficient since the integrator
and ADC energies are amortized over
more operations, and less computation is done
in the less efficient digital domain. Density also
improves since these circuits are shared by more
matrix elements. While smaller arrays can offer
better area utilization when mapping small matrices
[49, 65], large arrays are necessary to extract
the efficiency benefits of analog processing. Neural
networks that more fully utilize large arrays
will have superior system-level energy efficiency
when deployed in an analog accelerator.
3) Analog input bit accumulation yields a 2−4×
energy improvement. The technique increases
integrator energy, but reduces the number of
ADC conversions by 8×. When each input bit
requires a digitization step, the ADC dominates
the energy cost, as shown in Fig. 24(b) for
designs D and E; this is consistent with prior
work [11], [56].
For the reasons summarized in Section 9.2, systems
Figure 24. (a) core energy per operation (1 mac = 2 operations)
for various core configurations applied to an mVm of
size 1152×256. (b) Breakdown of energy use among core
components for selected configurations.
44
IEEE cIrcuIts and systEms magazInE
that rely on offset subtraction cannot exploit any of the
above techniques to reduce energy. Design A is the most
efficient design for differential cells, while Design E is an
offset-subtraction design that very nearly satisfies the
FPG (a pre-requisite for high accuracy using offset subtraction,
as explained in Section 6.3). Design E has 107×
higher energy consumption and 46× larger area. The
higher energy comes from having 4× as many bit slices,
8× as many ADC conversions per input value, and 16×
as many arrays to map a large matrix. The actual ratio
of energy consumption is smaller than the product of
these factors since only part of the total energy scales
with these factors.
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