IEEE Circuits and Systems Magazine - Q4 2022 - 45

Table 3.
Efficiency of selected core configurations.
A
Design
Negative values
Weight resolution
Bits / cell
# rows
Input bit S&A
ADC resolution
Ideal analog resolution Bout
Core area (mm2)
Core energy (fJ/op)
Diff.
8
7
1152
Analog
8
26.2
0.24
8.4
B
Diff.
9
1
1152
Analog
8
20.2
2.02
63.1
C
Diff.
8
7
144
Analog
8
23.2
1.30
43.3
D
Diff.
8
7
1152
Digital
8
18.2
0.27
25.8
E
Offset
8
2
72
Digital
8
8.2
11.14
902.0
Table 4.
ResNet50-v1.5 accuracy with SONOS errors using selected core designs ( 1000 images, 10 runs each).
C
A
76.3%
74.0%
±1.0%
B
75.3%
75.4%
±0.3%
75.4%
73.6%
±0.7%
D
76.3%
74.1%
±1.0%
Design
E
Ideal cells
SONOS
74.9%
50.2%
±5.3%
9.4. Accuracy Evaluation
Table 4 compares the ImageNet accuracy with
ResNet50v1.5 obtained using the same five design
points. The simulations include 8-bit weight and activation
quantization, 8-bit ADCs calibrated separately for
each design, and random SONOS programming errors
following the full state dependence in Fig. 22(b), sampled
ten times as described in Section 5.1. The small differences
in the baseline accuracy using ideal cells result
from the varying effectiveness of the 8-bit ADC calibration
across designs.
To keep the computations tractable, parasitic resistance
was not included. Relative to the SONOS cells, the
metal interconnects in the 40 nm process have a normalized
resistance of Rp
ˆ
d105. Fig. 21 shows that this resistance
has negligible effect on the accuracy of Designs
A, C, and D, which use differential cells and unsliced
weights. For the other designs, the accuracies in Table 4
are best-case estimates; with a realistic parasitic resistance,
the accuracy of Design B may be slightly lower,
and that of Design E is likely to be much lower.
The designs with differential cells and unsliced
weights (A, C, and D) all have similar accuracies, losing
roughly 2% on ImageNet by using SONOS cells. Design
B, which uses 1-bit slices,
is less sensitive to SONOS
errors than unsliced weights. This result is consistent

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