IEEE Circuits and Systems Magazine - Q4 2022 - 47

filamentary, and charge-based devices used for on-chip
learning and edge inference scenarios. At Sandia, he
explores these interests to yield reliable, interpretable,
and scalable future accelerator designs.
Venkatraman Prabhakar received the
B.Tech. degree from the Indian Institute
of Technology (IIT) Madras, India, and
the Ph.D. degree from the University of
California at Los Angeles in 1996. He is
in charge of SONOS technology development
at Infineon Technologies, USA. He has extensive
experience in integrating SONOS flash memories into
advanced technology nodes from 130nm down to 22nm.
Prashant Saxena, photograph and biography not available
at the time of publication.
Vineet Agrawal received the B.Tech. and
M.Tech. degrees from the IIT Madras in
2006. He is currently a Senior Design
Director at Infineon Technolo gies, USA,
where he works on developing ultra-low
power ML accelerators and differentiated
memory products. He has over 18 years of experience in
advanced memory design and technology development
and holds over 15 U.S. patents. His research interests
include the design and architecture of NVM based compute-in-memory
accelerators for edge AI applications.
Sapan Agarwal (Member, IEEE) received
the B.S. degree in electrical engineering
from the University of Illinois at Urbana-
Champaign in 2007, and the Ph.D. degree
in electrical engineering from the University
of California, Berkeley in 2012. He is
currently a Principal Member of Technical Staff at Sandia
National Laboratories, USA. He is interested in everything
from explainable machine learning algorithms and neuromorphic
systems to novel semiconductor devices.
Matthew J. Marinella (Senior Member,
IEEE) received the Ph.D. degree in electrical
engineering from Arizona State
University, Tempe, AZ, USA, in 2008.
He is currently an Associate Professor
with the School of Electrical, Computer,
and Energy Engineering, Arizona State University.
Before 2022, he was a Distinguished Member of the Technical
Staff with the Microsystems Center, Sandia National
Laboratories, where he led the Nonvolatile Memory Technology
Research and Development Program, and several
internal and externally funded research projects involvfourth
quartEr 2022
ing neuromorphic and low-power computing with emerging
electronic devices. He has authored or coauthored
over 100 peer-reviewed publications, given numerous
invited and contributed talks, and presented several
short courses on these topics. He has served in technical
and leadership roles in Laboratory- and DOE-level
initiatives on emerging computing. He is a member of the
SRC Decadal Plan Executive Committee, chairs Emerging
Memory Devices for the IRDS Roadmap, and serves on
various technical program committees.
References
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github.com/mlcommons/inference
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[3]
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[4]
S. Agarwal et al. (2017). CrossSim. [Online]. Available: https://crosssim.sandia.gov/
[5]
V. Agrawal et al., " In-memory computing array using 40 nm multibit
SONOS achieving 100 TOPS/W energy efficiency for deep neural network
edge inference accelerators, " in Proc. IEEE Int. Memory Workshop
(IMW), May 2020, pp. 1-4.
[6] A. Ankit et al., " PUMA: A programmable ultra-efficient memristorbased
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[7] M. Bavandpour, M. R. Mahmoodi, and D. B. Strukov, " Energyefficient
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[8] M. Bavandpour et al., " Efficient mixed-signal neurocomputing via
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IEEE cIrcuIts and systEms magazInE
47

https://github.com/mlcommons/inference https://github.com/mlcommons/inference https://github.com/mlcommons/inference/blob/master/calibration/ImageNet/cal_image_list_option_1.txt https://github.com/mlcommons/inference/blob/master/calibration/ImageNet/cal_image_list_option_1.txt https://github.com/mlperf/inference_results_v0.5/tree/master/open/NVIDIA https://github.com/mlperf/inference_results_v0.5/tree/master/open/NVIDIA https://cross-sim.sandia.gov/ https://cross-sim.sandia.gov/ https://keras.io

IEEE Circuits and Systems Magazine - Q4 2022

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