IEEE Circuits and Systems Magazine - Q2 2023 - 46

Digital FEx are easier to be implemented into a silicon chip than analog
approaches, offering shorter implementation time and easier
portability between different process nodes.
collected such that a frequency-selective feature vector
to be available. Alternatively, the switched-capacitor
(SC) BPFs were developed in [54] and [55] with a
parallel filter bank approach. As typically considered
in ∆Σ 68
[] and successive approximation register
(SAR) [69] ADC designs, the synchronous SC operation
comes with kT C/ noise-aliasing due to the DT
sample-and-hold. This attribute necessitates an antialiasing
filter and also a buffer stage ahead of the SC
filter both of which incur additional power and area
[69], although they were not actually implemented in
[54] and [55]. With this DT sample-and-hold environment,
capacitance must be increased to reduce the
kT C/ noise, but this choice comes with a larger
capacitor area, a higher switching power of the SC
operation, and a higher capacitive driving strength
required for the front-end buffer stage which results
in higher power consumption. In fact, the work in [54]
adopted high-density and low-leakage ferroelectric
capacitors to realize a low silicon area but it is typically
unavailable in standard CMOS process [70]. Also
note that the cascading approach of a LPF and a highpass
filter (HPF) to build a SC-BPF, adopted in [55],
exhibited a limited Q factor ().≤ 05
as discussed in
Fig. 6 and Eq. 8.
There are approaches to optimize the FFT-based
digital FEx design to reduce the power consumption toward
subµW. These designs implemented either a FFT
[56], [57] or a discrete Fourier transform (DFT) [10]
computation unit and this is typically followed by Mel
filtering and logarithmic compression circuits. These
digital FExs are easier to be implemented into a silicon
chip than analog approaches, as they can be automatically
place-and-routed from the RTL code such as
Verilog. Therefore, they offer simpler designs, shorter
implementation time, and easier portability between
different process nodes. In the KWS IC reported in [10],
the full signal chain starting from the analog front-end
(AFE) consisting of a voltage amplifier and a 10-bit
SAR ADC, to the digital backend consisting of a FFTbased
digital FEx and a RNN-based classifier is implemented
on-chip. The FEx alone consumed 733.Wµ or
40% of the total power 16 1. µW(). By using a serialized
FFT approach [57], the FEx power is reduced to only
340nW, however, it relied on an off-chip 16-bit ADC
46
IEEE CIRCUITS AND SYSTEMS MAGAZINE
which incurs additional power and area. Note that the
state-of-the-art 15.2 effective number of bits (ENOB)
∆Σ modulator with a 5kHz bandwidth (close to 4kHz
used in [57]) already consumes 45
.Wµ [71], [72] and
this power number did not include the power of the
decimation filter stage which is an essential building
block for the ∆Σ modulators in eliminating high-pass
shaped quantization noise. Therefore, it should be emphasized
that the actual power number of the 16-bit
ADC will be higher than 45
.Wµ in edge audio devices
operated in the real world. Note that we have not
covered digital designs of biquad filters in this manuscript,
e.g., the FPGA-based cochlea-inspired designs
in [73] and [74].
VII. Conclusion
This article introduces an overview of continuous-time
analog filters which have been used for audio edge intelligence
applications. A unified analysis of second-order
voltage-domain filters using the two-integrator-loop interpretation
is presented. With a review of several filter
architectures ranging from the OTA-based to source-follower-based
designs, gCm equivalents and small-signal
diagrams are summarized. The derived transfer functions
are also verified with the transistor-level simulations.
We provide a summary of the state-of-the-art audio
feature extraction circuits that have been used for
edge audio tasks, also with discussions of their current
challenges and design advantages.
There are a couple of interesting directions for future
analysis. One is the gain and stability analysis of
cascaded and parallel cochlea filter bank architectures
using the different filter designs [25]. The second is for
future detailed circuit analysis which considers the impact
of mismatch and circuit nonlinearities on the transfer
function of the different filter variants. For both studies,
one would require the specifications of a common
fabrication technology and the choice of power supply
voltage and transistor sizes for a fair comparison. However,
various studies have shown that deep networks
can learn to incorporate circuit nonlinearities and quantization
noise if these feature nonidealities are present
in the training samples of a network, similar to that carried
out in [14] and [38].
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IEEE Circuits and Systems Magazine - Q2 2023

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