IEEE Circuits and Systems Magazine - Q3 2023 - 23

Table 4.
MCUNet significantly improves the ImageNet accuracy on microcontrollers, outperforming the state-of-the-arts
by 4.6% under 256 kB SRAM and 3.3% under 512kB. Lower or mixed precisions (marked gray) are orthogonal
techniques, which we leave for future work out-of-memory (OOM) results are struck out.
Model/Library
Quant. MACs
MbV2 0.35× (r=144) [4] /
TinyEngine [8]
Proxyless 0.3× (r=176) [85] /
TinyEngine [8]
MbV1 0.5× (r=192) [5] /
Rusci et al. [45]
MCUNet (TinyNAS /
TinyEngine) [8]
MCUNet (TinyNAS /
TinyEngine) [8]
MCUNet-M4 (w/ patch)
MbV1 0.75× (r=224) [5]/
Rusci et al. [45]
MCUNet (TinyNAS /
TinyEngine) [8]
MCUNet (TinyNAS /
TinyEngine) [8]
MCUNet-H7 (w/ patch)
2) Experimental Results
Pushing the ImageNet Record on MCUs
With joint optimization of neural architecture and
inference scheduling, MCUNet significantly pushes
the state-of-the-art results for MCU-based tiny image
classification.
We compared MCUNet with existing state-of-the-art
solutions on ImageNet classification under two hardware
settings: 256 kB SRAM/1 MB Flash and 512 kB
SRAM/2 MB Flash. The former represents a widely used
Cortex-M4 microcontroller; the latter corresponds to a
higher-end Cortex-M7. The goal is to achieve the highest
ImageNet accuracy on resource-constrained MCUs
(Table 4). MCUNet significantly improves the ImageNet
accuracy of tiny deep learning on microcontrollers.
Under 256 kB SRAM/1 MB Flash, MCUNet outperforms
the state-of-the-art method [8] by 4.6% at 18% lower
peak SRAM. Under 512 kB SRAM/2 MB Flash, MCUNet
achieves a new record ImageNet accuracy of 71.8% on
commercial microcontrollers, which is 3.3% compared
to the best solution under the same quantization policy.
Lower-bit (int4) or mixed-precision quantization
can further improve the accuracy (marked in gray in
the table).
THIRD QUARTER 2023
int8
int8
mixed
int8
int4
int8
mixed
int8
int4
int8
24M
SRAM
Flash
STM32F412 (256 kB SRAM, 1 MB Flash)
308kB
38M
110M
68M
134M
119M
317M
292kB
<256kB
238kB
233kB
196kB
862kB
892kB
<1MB
1007kB
1008kB
1010kB
STM32H743 (512 kB SRAM, 2 MB Flash)
<512kB
126M
474 M
256M
452kB
498kB
465kB
<2MB
2014kB
2000kB
2032kB
Top-1
49.0%
56.2%
60.2%
60.3%
62.0%
64.9%
68.0%
68.5%
70.7%
71.8%
-
-
90.7%
Visual Wake Words under 32k KB SRAM
Visual wake word (VWW) reflects the low-energy application
of TinyML. MCUNet allows running a VWW
model with a modest memory requirement. As in Figure
14,2 MCUNet outperforms state-of-the-art method [8] for
both accuracy versus peak memory and accuracy versus
latency trade-off. Compared to per-layer inference,
MCUNet can achieve better accuracy using 4.0× smaller
memory. Actually, it can achieve >90% accuracy under
32 kB SRAM requirement, allowing model deployment
on low-end MCUs like STM32F410 costing only $1.6. Perpatch
inference also expands the search space, giving
us more freedom to find models with better accuracy
versus latency trade-off.
MCU-Based Detection on Pascal VOC
Object detection is sensitive to a smaller input resolution
[9]. Current state-of-the-art [8] cannot achieve
a decent detection performance on MCUs due to the
resolution bottleneck. MCUNet breaks the memory
bottleneck for detectors and improves the mAP by
double digits.
2Note that MCUNetV2 refers to the version w/ patch-based inference,
while MCUNet refers to per-layer inference.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
23
-
-
86.2%
Top-5
73.8%
79.7%
IEEE Circuits and Systems Magazine - Q3 2023

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