IEEE Circuits and Systems Magazine - Q3 2023 - 35

Feature
IMAGE LICENSED BY INGRAM PUBLISHING
Machine Learning
Hardware Design for
Efficiency, Flexibility,
and Scalability
Jie-Fang Zhang, Member, IEEE, and Zhengya Zhang, Senior Member, IEEE
Abstract
The widespread use of deep neural networks (DNNs) and DNNbased
machine learning (ML) methods justifies DNN computation
as a workload class itself. Beginning with a brief review of DNN
workloads and computation, we provide an overview of single instruction
multiple data (SIMD) and systolic array architectures.
These two basic architectures support the kernel operations for
DNN computation, and they form the core of many flexible DNN
Digital Object Identifier 10.1109/MCAS.2023.3302390
Date of current version: 11 October 2023
THIRD QUARTER 2023
accelerators. To enable a higher performance and efficiency,
sparse DNN hardware can be designed to gain from data sparsity.
We present common approaches from compressed storage
to processing sparse data to reduce memory and bandwidth
usage and improve energy efficiency and performance. To accommodate
the fast evolution of new models of larger size and
higher complexity, modular chiplet integration can be a promising
path to meet the growing needs. We show recent work on
homogeneous tiling and heterogeneous integration to scale up
and scale out hardware to support larger models of more complex
functions.
Index Terms-ML hardware, DNN accelerator, sparse DNN
architecture, DNN chiplet, heterogeneous integration.
1531-636X/23©2023IEEE
IEEE CIRCUITS AND SYSTEMS MAGAZINE
35

IEEE Circuits and Systems Magazine - Q3 2023

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