IEEE Circuits and Systems Magazine - Q3 2023 - 41

within the array, a systolic array requires a lower data
bandwidth. Systolic array is a data-driven architecture
and has a low control overhead. These factors contribute
to its high compute density.
Compared to a SIMD array, a systolic array is prewired
for a defined dataflow and it is thus less flexible.
A large-size systolic array provides a higher computation
capacity, but it may also suffer from a low utilization
when the operations do not utilize the entire array. The
long latency is another drawback of a large-size systolic
array.
TPU [13] is an example of systolic array. TPU is designed
with a matrix multiply unit (MMU) that consists
of a systolic array of 256 × 256 PEs. Fig. 8(a) and (b) show
TPU's system architecture and dataflow in the MMU, respectively.
The weight data are loaded from the weight
FIFO into the MMU, and a systolic data setup module
organizes the input data to ensure proper accumulation
of the psums in the MMU. The MMU operates similarly
to the description above where inputs are streamed in
from the left to the right, and the psum accumulation
happens vertically across columns.
Table 1 compares the SIMD architecture to the systolic
array architecture. A SIMD array can be in the form
of a 1D PE array to support VMM operations, and it can
also be scaled up to a 2D PE array to support MMM
operations. A systolic array is commonly designed as
a 2D PE array to support MMM operations. In terms of
data movement, a SIMD array needs to access memory
to feed all its PEs, whereas a systolic array can rely on
neighboring PE connections to reduce the bandwidth
requirement and the number of memory accesses. A
systolic array has a lower control overhead and can be
easily scaled up. As such, a systolic array provides a
Figure 7. Illustration of the operations on systolic array: (a) input and weight matrices, (b) weight data configuration, (c) input
streaming (early-stage), (d) input streaming (general), and (e) output collection.
THIRD QUARTER 2023
IEEE CIRCUITS AND SYSTEMS MAGAZINE
41

IEEE Circuits and Systems Magazine - Q3 2023

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