IEEE Circuits and Systems Magazine - Q3 2023 - 42

Figure 8. Illustration of the TPU (a) system architecture and (b) matrix-multiply engine architecture. Adapted from [13] ©2017 ACM.
Table 1.
Processing architecture summary.
SIMD Array
Architecture
Operations
Data
movement
Compute
density
Flexibility
Hardware
Utilization
1D/2D PE array
with shared
instructions
VMM, MMM
More memory
access
Lower
Higher
Higher
Systolic Array
2D PE array with
neighboring
connectivity
MMM
Mostly local
data movement
Higher
Lower
Lower
higher compute density than a SIMD array. On the other
hand, a systolic array is often designed for a fixed computation,
whereas a SIMD array is more flexible to support
a wide range of operations. The higher flexibility
of a SIMD array over a systolic array leads to a higher
hardware utilization, e.g., in flexibly handling inputs of
various shapes.
C. Stationary Dataflows
DNN computation can be mapped onto the processing
architectures in two common ways: weight stationary
(WS) and output stationary (OS). These mapping methods
provide data reuse opportunities and dictate the
computation dataflows.
Weight Stationary (WS) Dataflow: In the WS dataflow,
a PE stores a weight locally and reuses it for MAC
42
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Figure 9. Illustration of (a) weight-stationary dataflow and
(b) output-stationary dataflow. Adapted from [21] ©2017 IEEE.
computation with as many inputs as possible. The WS
dataflow can effectively reduce the number of memory
accesses required to fetch weights from memory, leading
to a lower memory bandwidth and a lower power
consumption. An example WS dataflow on a systolic array
architecture is illustrated in Fig. 9(a). In the example,
the weights WWWW
() are cached locally in
012 3
,, ,and
the PEs. Inputs are accessed from memory and sent to
the corresponding PEs for computation. The computed
psums are passed along the PE array for accumulation.
Lastly, the output data is written back to memory. The
THIRD QUARTER 2023

IEEE Circuits and Systems Magazine - Q3 2023

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