IEEE Circuits and Systems Magazine - Q3 2023 - 48
performance and efficiency without excessive hardware
overhead [27], [40].
Different forms of sparsity are compared in Fig. 18. If
pruning [24] is done without any constraints, it results in
unstructured sparsity shown in Fig. 18(a). Pruning without
any constraints generally produces a higher sparsity,
but processing unstructured sparsity requires more
fine-grained control and can cost excessive hardware
overhead. Pruning can be done by block with a density
upper bound. The approach produces density-bounded
block sparsity [19], [41]. For example, Fig. 18(b) shows
the result of a density-bounded block pruning with each
13× block containing at most one nonzero value. Pruning
can be done by block [42], [43], e.g., by 22× blocks as
shown in Fig. 18(c). Pruning can even be done by input
and output channel [40], [44], [45] as shown in Fig. 18(d).
More coarse-grained pruning produces more hardwarefriendly
structured sparsity, but it may sacrifice the
model accuracy to some degree.
One well-known example that leverages the densitybounded
block sparsity is Nvidia A100 GPU [19]. As illustrated
in Fig. 19, fined-grained structured pruning is
applied to the trained model weights to create the socalled
2:4 sparsity, i.e., a 50% density bound for each
block of 14× data. The sparse weights are compressed
with COO indices that are used to access the dense inputs
in processing, similar to the illustration in Fig. 13(b).
H. Bit-Level Sparsity
Besides sparsity at data level, bit-level sparsity can also
be leveraged by bit-serial multipliers. One example that
adopts this approach is bit-pragmatic [46], where the
zero bits in one of the operands can be skipped in bitserial
multiplication. The bit-pragmatic processing is
illustrated in Fig. 20 [46]. The IA is processed in a bitserial
fashion, and each nonzero bit is encoded by its
position in the bit sequence similar to the COO format.
In computation, the nonzero bit position of each IA data
is used to set the configurable left shifter to shift the
W data value, effectively acting as a bit-wise multiplier.
Exploiting sparsity in bit-level reduces the number of
computation cycles, and can increase both efficiency
and throughput.
Figure 18. Common sparsity types: (a) fine-grained, (b) density
structured, (c) block structured, and (d) filter structured.
I. Sparse Architectures for RNNs and Transformers
Compared to the sparse architectures for CNNs, the
sparse architectures for RNNs are focused on improving
the performance for sparse matrix vector multiplication
(SpMV) and the element-wise operations associated to
Figure 19. Processing mechanism of Nvidia A100 GPU for fine-grained structured sparse model weights. Adopted from [19].
48
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2023
IEEE Circuits and Systems Magazine - Q3 2023
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