IEEE Circuits and Systems Magazine - Q3 2023 - 49

the type of RNNs. For instance, LSTM requires elementwise
multiplication, sigmoid, and tanh operations to
compute the outputs. ESE is an example of a sparse architecture
for LSTM [47]. It proposes a load-balancing
pruning technique to reduce the workload imbalance in
the sparse inputs and weights during pruning. Similar
to EIE [33], ESE adopts the CSC format to store and compute
the sparse data.
Different from the pruning techniques that eliminate
the unimportant weights and inputs
in CNNs to RNNs, the sparse architectures
for transformers proposed
to prune the unimportant connections
(tokens or heads) in the selfattention
matrix [48], [49]. Fig. 21
presents an example of the attention
matrix. Several tokens have small
contributions to the final result, thus
can be pruned away without performance
degradation. Spatten [48]
proposed cascade head and token
pruning techniques to eliminate the
tokens and heads in the attention
matrix. It uses a shifting mechanism
to avoid irregular memory access
from the sparse computation and a
reconfigurable adder-tree to leverage
the sparsity for speedup. DOTA
[49] trains a decoder side by side to
the Transformer to detect the weak
connections in the attention matrix.
To process the sparse attention matrix,
DOTA adopts an out-of-order
processing scheme to leverage the
temporal locality and avoid unnecessary
memory accesses.
V. Scale Up and Scale Out
The DNN model complexity grows at
1.5 times annually [8], [9], [29], [50],
but it is unlikely to expect new custom
chips to be built to respond to
the rapid evolution of DNN models at
the same rate. This lag is attributed
to the high cost and effort to design
new chips, especially ones that utilize
large silicon area and advanced
technology nodes needed to support
the processing of more complex DNN
models. Other important factors include
the diverse use cases of DNN
that diminish the space for custom
THIRD QUARTER 2023
chips, and the rapid evolution of DNN models that shortens
the useful life of such custom chips.
Domain-specific accelerators for DNN, such as
NVDLA [51] and TPU [13], represents a path forward
by providing some degree of flexibility to support not
only current models but also future models. However,
without growing the raw compute and memory capacity,
the performance of such accelerator will not be able to
meet the demands of newer and more complex models.
Figure 20. Frontend mechanism and processing example of bit-pragmatic [46]: (a)
IA and W data for processing and (b) bit-serial processing using IA's nonzero bit
position to control the shifter.
Figure 21. Illustration of the attention matrix with unimportant
from [48].
tokens. Adopted
IEEE CIRCUITS AND SYSTEMS MAGAZINE
49

IEEE Circuits and Systems Magazine - Q3 2023

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