IEEE Circuits and Systems Magazine - Q3 2023 - 54

Feature
Challenges in Precision
Continuous-Time
Delta-Sigma Data
Converter Design
Raviteja Theertham, Member, IEEE, and Shanthi Pavan, Fellow, IEEE
Abstract
We describe challenges encountered in the design of continuoustime
delta-sigma modulators that target high resolution (>16 bits)
over wide bandwidths (several hundreds of kHz). The linearity of
the feedback DAC and flicker noise introduced by the loop filter
are primary problems that need to be addressed. We describe
two techniques that are inherently more linear than prior-art DACs,
namely the virtual-ground-switched resistor DAC and the zapped
Digital Object Identifier 10.1109/MCAS.2023.3302391
Date of current version: 11 October 2023
54
IEEE CIRCUITS AND SYSTEMS MAGAZINE
1531-636X/23©2023IEEE
THIRD QUARTER 2023
virtual-ground-switched dual
return-to-open DAC. Flicker noise
can be eliminated by chopping, but one needs to pay careful attention
to minimize chopping artifacts. Example multi-bit and singlebit
designs achieving in excess of 100 dB SNDR over a 250 kHz
bandwidth, designed in a 180 nm CMOS technology, are used to
illustrate the efficacy of the techniques described in this article.
Index Terms-Intersymbol intereference, flicker noise, wideband,
precision, jitter, low-distortion, data-weighted averaging,
noise shaping, resistor DAC, chopping, FIR DAC.
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IEEE Circuits and Systems Magazine - Q3 2023

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