IEEE Circuits and Systems Magazine - Q3 2023 - 56

Target
130
140
150
160
170
180
High resolution & power
efficient CTDSMs over audio
and lower BW
Noise + Distortion Spectral Density = -(SNDR_max + 10log(BW)) (dBFS/Hz)
-160
CTDSMs > 15 bits ENOB
All CTDSMs
-150
-140
-130
as a function of the NDSD for all CTΔΣMs presented at
the International Solid-State Circuits Conference (ISSCC)
and Symposium on VLSI Circuits (VLSI) (data from
[4]). From the figure, we observe that achieving a high
Schreier FoM is difficult, and particularly so if the NDSD
is also low2 (notice that there are very few data points
towards the top-left corner of the figure).
The data points in blue in Fig. 2 correspond to high-120-110
Figure
2. Schreier SNDR FoM as a function of in-band
(noise + distortion) spectral density for all CTΔΣMs presented
at the International Solid-State Circuits Conference (ISSCC)
and Symposium on VLSI Circuits (VLSI) (data from [4]).
continuous-time signal chain does not require an explicit
input driver or anti-alias filter. Consequently, the
PGIA can directly drive the modulator's input. Furthermore,
the external precision reference can be directly
interfaced to the ADC as the CTΔΣM draws only a static
current from its reference pins. From the discussion
above, it is apparent that the board area and bill of materials
(BOM) can be greatly reduced when a CTΔΣM is
employed [3]. An apple-to-apple comparison of discreteand
continuous-time signal chains is shown in Fig. 1(c),1
where the ADCs are designed to achieve 104 dB SNDR
in a 125 kHz bandwidth. We see that the CTΔΣM-based
chain occupies a board-area that is about a third of the
discrete-time chain.
A CTΔΣM resolution in excess of 17 bits over a bandwidth
of 250 kHz translates to an in-band noise spectral
density lower than −158 dBFS/Hz. As with all engineering
efforts, it helps to see " what is out there " in this space.
To that end, we benchmark existing CTΔΣMs along two
performance axes-the in-band noise + distortion spectral
density (NDSD) and power efficiency. The NDSD,
which quantifies the power of in-band noise and distortion
(normalized to signal bandwidth), is given by
NDSD ()+ ()10 logBWdBFSHz
=− SNDRmax
/
(1)
where the SNDR is in dB and the bandwidth (BW) is in
Hertz. The power efficiency is quantified by the Schreier
FoM, calculated as
FoMmax


SchreierSNDRlog=+10
BW
P



(2)
where the SNDR is in dB, BW is in Hertz, and P is the
power dissipated in Watts. Fig. 2 plots the Schreier FoM
1Picture courtesy of Analog Devices Inc., from Analog Dialogue, vol. 54,
August 2020.
56
IEEE CIRCUITS AND SYSTEMS MAGAZINE
II. Architectural Choices
The first choice that the designer needs to be make is
that of the number of quantizer levels to be used. Multibit
and single-bit designs have their compelling advantages
(and drawbacks!). A multi-bit modulator can have
a maximum stable amplitude (MSA) that is almost full
scale, is less susceptible to nonlinearities in the loop filter
and to clock jitter. The amount of hardware needed
2Data points towards far right in Fig. 2 having low FoM despite the relaxed
NDSD correspond to some of the early works realized in >0.5 µm
technology nodes.
THIRD QUARTER 2023
resolution CTΔΣMs (>15 ENOB). It turns out that these
state-of-the-art designs [5], [6], [7], [8], [9], [10], [11]
achieve high resolution over audio (or lower) bandwidth.
We deem a design as being " power efficient " if it
achieves a Schreier FoM greater than 170 dB. By this definition,
we see that prior work on power-efficient, high
resolution CTΔΣMs has been limited to low bandwidth.
Targeting high power efficiency and high SNDR over a
bandwidth that is about 10× higher (NDSD about 10 dB
lower) than prior art brings to light several issues that
are usually not problematic in CTΔΣMs targeting less
aggressive performance metrics. The challenges are
especially severe since such converters are designed in
legacy CMOS (to keep cost low).
The aim of this article is to describe the key challenges
and discuss some potential solutions to these
problems. It is organized as follows. Throughout the
article, we explain the challenges and solutions in
the context of multi-bit and single-bit CTΔΣM designs
with a peak SNDR target of about 105 dB in a 250 kHz
bandwidth, designed in a 180 nm CMOS process. Section
II describes the architectural choices available
to the designer, and the relative merit of single- and
multi-bit ΔΣ loops in the context of high-resolution
CTΔΣMs. It turns out that the linearity of the feedback
DAC and flicker noise of the loop filter are key problems
that need to be addressed. These issues and
solutions are described in Sections III and IV, respectively.
Section V summarizes some key circuit-design
aspects. Measurement results from [12] and [13] are
summarized and compared in Section VI. Section VII
concludes the article.
Schreier FoM
(SNDR_max + 10log(BW/P)
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