IEEE Circuits and Systems Magazine - Q3 2023 - 57

to realize a multi-bit ADC
and DAC, however, increases
exponentially with the quantizer
resolution. Furthermore,
much attention needs
to be paid to mitigate the effect
of element mismatch in
the feedback DAC. A singlebit
modulator, on the other
hand, needs a higher OSR
to achieve the same in-band
quantization noise, has a
lower MSA and is problematic
with respect to loop-filter
linearity and clock jitter.
However,
the ADC design
is (almost) trivial, and the
feedback DAC is inherently
linear.
The benefits of multibit
and single-bit operation
can be achieved in a single
architecture by using FIR
feedback.
It
is
a
generic
technique that increases the
effective number of levels in the feedback DAC output,
thereby reducing the susceptibility of the modulator to
clock jitter and nonlinearities in the loop filter. It has
been successfully applied to both single- and multi-bit
designs.
Fig. 3 shows the simplified multi-bit and single bit
architectures of CTΔΣMs designed to have a peak inband
SQNR > 118 dB. The former (in Fig. 3(a)) needs to
be clocked at 32 MHz, while the latter (in Fig. 3(b)) needs
to run at 48 MHz. The loop filter in both the architctures
is chosen to be of the CIFF-B type [14], [15]. Such
a topology decouples the fast path around the quantizer
(through I1) and the high precision path (through
DAC2,I2,I3,I4,I1). The zeros in the noise transfer function
(NTF) are realized by weak resistive feedback around
I2-I3 and I4-I1 (not shown explicitly in Fig. 3 to reduce
clutter). The input u is fed forward into I1; this makes
the swing at the output of I4 largely independent of u. All
integrators are realized using active-RC techniques to
achieve high linearity. RC time-constant variations are
addressed by the use of digitally switchable resistor and
capacitor banks. It turns out, as we discuss later, that
flicker noise is a serious problem in CTΔΣMs targeting
low in-band NDSD. Chopping is an attractive technique
to address this issue. The first stage of the OTA used in
I2 is chopped at fc to achieve an in-band spectrum with
a low flicker noise corner. The considerations for choosing
fc are discussed in Section IV-A.
THIRD QUARTER 2023
Figure 3. Simplified high-level architecture of the CTΔΣM. (a) Multi-bit quanitzer. (b) Singlebit
quantizer.
Figure 4. Amplitude sweep of CTΔΣM with static DAC level
mismatch involving a 9-level quantizer running at an OSR of
64. Amplitude sweep for a single-bit CTΔΣM with an OSR of
96 is also shown for comparison.
The multi-level modulator (in Fig. 13(a)), which uses
a 9-level quantizer and an NTF with an out-of-band gain
(OBG) of 1.5, results in an MSA of about −0.3 dBFS. An
8-tap FIR DAC increases the effective number of levels
in the feedback DAC waveform to about 70, which
allows this CTΔΣM to tolerate a (white) clock jitter of
about 10 ps rms. This level of jitter tolerance is overkill,
however, since a crystal oscillator can easily achieve an
rms jitter of less than 1 ps. The FIR DAC DAC2() is resistive
to achieve low noise and is realized using semidigital
techniques. All the weights of the FIR filter Fz
are chosen to be identical. DAC1 and Fzc () form the
()
IEEE CIRCUITS AND SYSTEMS MAGAZINE
57

IEEE Circuits and Systems Magazine - Q3 2023

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