IEEE Circuits and Systems Magazine - Q3 2023 - 58

compensation FIR DAC, which feeds into I1. Its taps are
computed using the theory given in [16].
Data weighted averaging (DWA) [17] is used as
the DEM technique to address mismatch in the feedback
DAC elements. Simulations show that for a fullscale
input, DWA can handle DAC element mismatch
of σ = 02
.% without degrading the in-band linearity.
However, DWA results in several spurious tones at low
input amplitudes [18], causing a kink in the dynamicrange
plot, shown in Fig. 4. The figure plots the SNDR
versus input amplitude for 30 Monte Carlo runs. We see
kinks in the SNDR for almost all runs. The root cause
of this is element-rotation tones that appear in-band
over a range of (small) inputs, as seen from the spectrum
in the inset of Fig. 4. Two observations are in order
here. First, the kink in the DR plot would not be prominent
in designs that attempt a lower resolution, as the
DWA tones would be largely masked by thermal noise.
Second, tones could be avoided by using higher-order
mismatch-shaping techniques [15]. Shi et al. [19] implemented
vector-quantizer based second-order DEM (in
40 nm process) to mitigate the SNDR kink and relax the
matching requirement of the feedback DAC elements.
These algorithms, however, are hardware and power
intensive. In the 180 nm technology used in this case
study, simulations indicate that the logic needed to
implement second-order noise shaping would consume
upwards of 10 mW.
As seen above, the multi-bit architecture is attractive
from a viewpoint of MSA and loop-filter linearity.
However, the ADC and feedback DAC are complex and
should be expected to consume significant amounts
of power. This is the motivating reason to consider
single-bit conversion, in spite of the lower MSA. The
hope is that the power saved in the digital portion
of the CTΔΣM compensates for the increased power
needed in the loop filter. FIR feedback reduces the
step size of the feedback DAC waveform, which not
only relaxes I2's linearity requirements but also reduces
the susceptibility of the modulator to clock
jitter. The work in this case study uses a 12-tap FIR
DAC F(z) − DAC2 with identical tap weights in the main
feedback path. Calculations show that the CTΔΣM
can tolerate an rms white jitter of 1 ps which is easily
achievable with a crystal-oscillator based clock generator.
As with the multi-bit design, FIR feedback also
facilitates chopping the input integrator in artifactfree
manner. The half-clock-cycle delay of the quantizer,
as well as the delay due to the 12-tap FIR in the
main DAC is compensated by a 10-tap FIR filter Fzc ()
placed in the direct path (through DAC.0 ) It turns out
that Fzc ()− DAC0 and the summer can be implemented
in a single unit in an extremely
power- and area-efficient manner using
passive techniques. This is made
possible with single-bit design as the
attenuation at the input of the quantizer
is of no consequence as long as
the comparator regenerates faithfully
within half a clock cycle.
III. Feedback DAC Considerations
The main feedback DAC and its interface
with the input integrator (DAC2
and I2 in Fig. 3(a) and (b)) is the most
critical part of the design. Resistive
feedback DACs are the preferred
choice
in CTΔΣMs targeting low
Figure 5. Mechanism of distortion due to parasitic resistance Rpar in the reference
path of a conventional resistive DAC. (a) Resistive DAC with parasitic
capacitance cp of the switches. (Inset shows multi-bit ADC + DAC and single-bit
FIR DAC interface.) (b) Quantizer output code, and number of transitions at output
of the DWA logic for a (MSA-0.5) dBFS sine-wave input. (c) FIR filtered output
code, v∗hfir, and number of transitions in the FIR delay chain for the same input.
58
IEEE CIRCUITS AND SYSTEMS MAGAZINE
noise. The efficacy of switched-resistor
NRZ DACs has been successfully
demonstrated in several state-of-theart
high resolution audio CTΔΣMs
[6],
[20], [21]. Unfortunately, when
the bandwidth and resolution are
increased by 10× and 10 dB, respectively,
the conventional approach,
where the resistors are switched at
the reference, is not suitable. The
THIRD QUARTER 2023
IEEE Circuits and Systems Magazine - Q3 2023

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2023
