IEEE Circuits and Systems Magazine - Q3 2023 - 60

modulate the resistance of the virtual-ground switches,
resulting in second-harmonic distortion. The inset in
Fig. 7 shows the simulated HD2 as a function of phase
imbalance for the multi-bit design. It is seen that the
phase imbalance between ip and im should be <0.1°
to achieve THD < 110 dB. This is extremely difficult to
achieve in a practical test setup.
A solution to address the problem of imbalanced inputs
is to use common-mode feedback (CMFB) circuitry
at the OTA input, drawn in red in Fig. 7(a). CMFB forces
the common-mode component of the virtual-ground
nodes to 05. Vref ,
even with imbalanced differential
inputs. Consequently, distortion that would otherwise
occur due to the input-dependent modulation of the
DAC-switch resistance is reduced.
The virtual-ground switched-resistor DAC described
above is a vast improvement over a conventional DAC
which is reference switched. Unfortunately, however,
mismatch between the resistance of the through- and
cross-switches, namely M1/M4 and M2/M3 in Fig. 8(a)
respectively results in distortion. We skip the details
here, but it turns out that the parasitic capacitances
cc12 at nodes a and a ˆ inject a datapp
cp()/=+()
13
dependent error charge into the integrator. The magnitude
of this charge can be shown to be proportional
to ∆Rc
sw p where ∆Rsw denotes the mismatch between
the resistances of the through- and cross-switch pairs.
∆Rsw not only arises due to threshold mismatch of the
transistors, but mismatch between the resistance of the
switch interconnections. Fig. 8(c) shows the effect of
∆Rc
sw p on the distortion of the converter. While these
challenges can be overcome, our experience with [12]
indicated that the DAC had to be laid out very carefully,
and be simulated after extracting resistance of the interconnect,
and iterating this procedure multiple times.
Several layout considerations to reduce the impact of
interconnect resistance from the DAC to the virtualground
are discussed in [23].
B. The Zapped Virtual-Ground-Switched Dual
RTO DAC
From the discussion above, we saw that NRZ DACs,
however carefully designed, are fundamentally prone to
data-dependent errors. A return-to-zero (RZ) DAC is inherently
immune to ISI since error due to rise-fall asymmetry
is data-independent [24], [25]. However, such a
DAC suffers from jitter and linearity problems due to the
large steps of the RZ pulse. When implemented with resistors,
an RZ DAC has the additional problem of higher
thermal noise, since it injects noise even when the DAC
current is zero. An improvement that addresses these
problems is the dual return-to-open (RTO) DAC [26]. The
basic idea behind such a structure is to create an NRZ
DAC pulse by expressing it as a sum of two RZ pulses,
Figure 7. (a) Mechanism causing distortion due to an
imbalanced input. (b) Output PSD with 1° phase imbalance
between ip and im. The inset shows HD2 as a function of
phase imbalance.
60
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Figure 8. Illustration of distortion due to on-resistance
mismatch. (a) Schematic of virtual-ground switched DAC.
(b) Example drive bit waveforms and injected error charge
(c) HD2 as a function of switch on-resistance mismatch
(R = 450 Ω, fs = 48 MHz).
THIRD QUARTER 2023
IEEE Circuits and Systems Magazine - Q3 2023

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