IEEE Circuits and Systems Magazine - Q3 2023 - 61

where one is delayed with respect to the other by halfclock
cycle. Like their NRZ cousins, conventional dual
RTO DACs have been switched at the reference end. As
discussed in [12], however, the distributed capacitance
of the resistors results in increased distortion. Moving
the switches to the virtual-ground side improves performance,
as described below.
Fig. 9 shows the basic idea behind the virtual-groundswitched
dual return-to-open (DRTO) DAC [13]. vgp and
vgm denote the virtual-ground nodes of the differential
OTA. The DAC is composed of unit cells, with a unit
cell comprising of two RTO DACs DACa
(
and DAC,b )
each of which is active for half-clock cycle. They work
in a complementary fashion to effectively create an NRZ
DAC pulse. The call out in Fig. 9 shows the schematic
of DACa which is active when clk is high. During this
phase Dap and Dam are complementary and take on
values 0/1 depending on the data-bit D, while the signal
zap a is low. Since vgp and vgm
have a commonmode
voltage of 12/() ,refV the differential current that
flows into the integrator is given by ±VR
ref /2 . Thanks
to switching at the virtual-ground, only NMOS switches
are necessary. This greatly simplifies the layout and
the driving logic compared to a reference-switched
RTO DAC [26]. The common-mode voltage of the virtual
ground nodes is held at 12/()Vref by a CMFB loop (not
shown in Fig. 9).
When clk goes low, DACa is in its " open " phase,
where DD are at ground. As soon as the DAC enap
am,
ters this phase, nodes a and â attain potentials Vref
and 0, respectively. Thus, the parasitic capacitors cp1
and cp2 corresponding to node a are charged to Vref ,
while those corresponding to â are charged to ground.
To motivate the need for the zap switch, assume for the
time being that it does not exist. Then, as soon as DACa
attempts to enter the active phase from the open phase
at the rising edge of clk, the parasitic charge on these
capacitors would be steered into the integrating capacitors
depending on the data-bit D. The resulting datadependent
spike of current needs to be absorbed by the
OTA, and this causes in an increased swing at the OTA's
virtual-ground nodes, resulting in distortion. The zap
switch in Fig. 9 avoids this problem, as described below.
zapa is high for a small interval at the end of DACa's
" open " phase, and shorts nodes a and â together. This
way, the potentials at these nodes attain 12/()Vref at the
end of the zap phase. Consequently, the cp1 and cp2 do
not inject charge into the integrator at the beginning of
the DAC's active phase. The width of the zap phase is
exaggerated in Fig. 9 for clarity-in practice, it is only a
few inverter-delays wide.
The noise of the DAC has a significant bearing on the
SNR of the modulator. As discussed earlier, an advantage
THIRD QUARTER 2023
of the RTO structure (as opposed to a resistive RZ DAC) is
that it does not add thermal noise when it is open. Thus, as
far as thermal noise is concerned, the noise of a dual-RTO
DAC should be expected to be identical to that obtained
with a resistive NRZ DAC supplying the same current.
IV. Addressing Flicker Noise
Having described problems with feedback DACs and
potential solutions, we discuss the next " show-stopper "
issue, namely flicker noise. The low-frequency precision
of a CTΔΣM is limited by its flicker noise, which is predominantly
due to the input stage of the OTA used in
the input integrator (I2 in Fig. 3). The brute-force way
of addressing 1/f noise is to use large device sizes. Unfortunately,
this is impractical in designs that target a
very low thermal noise floor as the resulting (parasitic)
capacitance at the OTA's virtual ground is much larger
than the integrating capacitance used in I2. This parasitic
reduces the high-frequency feedback factor around
the OTA, thereby greatly reducing integrator speed, and
consequently its linearity.
Chopping is an alternative way of mitigating 1/f noise,
and has been applied in several state-of-the-art audio
CTΔΣMs [6], [22]. The basic idea is to chop the first stage
of the OTA in the input integrator, as shown in gray in
Fig. 10. The parasitic input and output capacitances of
the stage are modeled by c1 and c2, respectively. Since
chopping modulates the OTA's flicker noise out of the
signal band, small input devices can be used, resulting
in a low parasitic capacitance at the OTA's input. Unfortunately,
chopping causes the integrator to become a
Figure 9. Simplified schematic and timing of
ground switched dual return-to-open (DRTO) DAC.
the virtualIEEE
CIRCUITS AND SYSTEMS MAGAZINE
61
IEEE Circuits and Systems Magazine - Q3 2023

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2023
