IEEE Circuits and Systems Magazine - Q3 2023 - 63

its input voltage must be zero. This way, the input and
output nodes of the chopped input transconductor
gm1, namely 1 and 2 settle to zero. As a result, using
a three-stage feedforward-compensated OTA with a
chopped input stage, and adequately large bandwidth,
should not result in chopping artifacts. In practice, however,
the voltages at nodes 1 and 2 will be non-zero
owing to finite gain of the transconductors, as shown in
the call out of Fig. 12(a).
Simulations of a fourth-order CTΔΣM with a 9-level
quantizer, but without FIR feedback were run to estimate
chopping artifacts. The input integrator used a threestage
OTA (whose circuit design details will be discussed
in the next section) with a chopped input stage.
The chopping frequency was chosen to be ff
cs= /16.
The results are shown in Fig. 12(b). We see that the inband
SQNR decreases only by about 3 dB, indicating
that the power of the aliased noise due to chopping is
about the same as the quantization noise. Fortunately,
owing to the 8-tap FIR feedback used in our design,
chopping artifacts are reduced by a further 20 dB, resulting
in virtually no degradation of in-band noise due
to chopping. The reason for this is the following. The
8-tap FIR DAC creates spectral nulls in the feedback
waveform at multiples of fs /8. Since ff
cs= /16, aliasing
of shaped noise, which occurs from around multiples
of 28
ff
cs= /
is greatly attenuated. FIR feedback, apart
from reducing jitter sensitivity and improving loop filter
linearity, also enables the use of chopping in an artifactfree
manner [6], [22].
B. Simulation Challenges
A practical aspect that arises during the design process
is the following. PVT variations will cause the OTA gain
and bandwidth to vary, thereby resulting in a variation
of chopping artifacts. It is necessary to be able to estimate
" chopping noise " across PVT corners, and ensure
that it is well below the thermal noise floor of the converter.
Running a transient analysis on the entire modulator,
which is not only time consuming. As the target NSD
is very low, the simulation record length of at least 8 K
points are necessary in order to reliably estimate the inband
noise. Conventional transient analysis is impractical
as it is unable to separate the quantization and chopping
noise components. We therefore developed a rapid
way of estimating chopping noise without having to run
long transient simulations-the details are given in [22].
V. Circuit Design for Multi-Bit and
Single-Bit Prototypes
In this section we describe the circuit design techniques
employed in the example multi-bit [22] and
THIRD QUARTER 2023
Figure 12. (a) OTA-RC integrator with a three-stage feedforward-compensated
OTA. (b) The responses of the chopped
nodes to an NRZ DAC pulse: after an initial transient, nodes 1
and 2 almost settle to zero. (c) Simulated output PSD of a
fourth-order CTΔΣM using a three-stage OTA in the input
integrator with chopping on/off. FIR feedback is not used for
these simulations.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
63
single-bit [13] designs achieving in excess of 100
dB SNDR over a 250 kHz bandwidth. Fig. 13(a) and
(b) shows the simplified single-ended schematic of
the fourth-order CTΔΣM where negative component
values (in the inset of Lct
())s
indicate inversion in
the fully-differential version. In the multi-bit design
(Fig. 13(a)) 9-level quantizer and the 8-tap FIR filter,
results in 72 effective levels in the feedback DAC.
The main feedback DAC in the single-bit design (refer
Fig. 13(b)) is a resistive 12-tap FIR structure that uses
dual-RTO unit cells. All integrators are realized using
active-RC techniques. I3, I4, and I1 are impedancescaled
to reduce power dissipation. Consequently,
the currents injected by the taps of the compensating
FIR DAC Fzc () are small. A resistive compensating
DAC would occupy a large area. This is avoided
by realizing it using current-steering techniques in
the multi-bit design and capacitive DAC in single-bit
design. The low-frequency current injected by DAC
connecting v2 is compensated by the feed-in path
through Rk1, and consequently reduce the size of
C4 that would otherwise be needed. The component
values accounting for finite integrator gain, parasitic
poles and excess loop delay are derived by using
the numerically-robust design-centering technique
of [28]. The OTA used in I2, shown in Fig. 13(c), is a
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