three-stage feedforward-compensated design, whose input stage is chopped. Other OTAs are two-stage feedforward compensated structures. The FIR compensation in the single-bit design is done using passive summation around the quantizer (shown as colored part in Fig. 13(b)). As a result, the attenuated version of the loop filter output is presented at the input-pair of the quantizer which samples on the falling edge of the clock. To give it sufficient time for regeneration, DAC1 and the main FIR DAC are clocked using the rising edge, resulting in an excess delay of half-clock cycle. A. OTA Design Details The simplified schematic of the input OTA is given in Fig. 13(b). The three-stage architecture achieves high dc gain and results in reduced chopping artifacts (as discussed in Section IV). The input stage reuses current to achieve a large gm for a given bias current. Cascodes are used to increase dc gain of the stage, and to reduce the parasitic capacitance at nodes 2 and ′2 by shielding these nodes from the large parasitics of the input pairs. Cx added at the output of the first stage's chopper slows down the third-order path through gg gmm m12 3 ---, to ensure adequate phase margin. The subsequent stages gg ggmm mm24 35 save power. The first-order path formed by gm5 is accoupled to increase the maximum-permissible swing at the OTA's output. B. Quantizer and Compensation FIR DAC The ADC in the multi-bit design uses a flash architecture, with the comparators being implemented using StrongArm latches. The 1-bit quantizer in single-bit () are employ current reuse to Figure 13. Simplified single-ended schematic of the modulator. (a) Multi-bit design. (b) Single-bit design. (c) Simplified schematic of the three-stage feedforward-compensated OTA used in the input integrator (I2). The first stage of the OTA is chopped at a frequency fc = fs = (2× # FIR taps).(d) Quantizer and implementation of direct path using capacitive summation in single-bit design. 64 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2023