IEEE Circuits and Systems Magazine - Q3 2023 - 65

The compensation DAC and quantizer occupy very little space.
This approach is fundamentally made possible due to
single-bit operation.
design is also implemented using the StrongArm latch.
After regeneration, the outputs of the latch are held for
the rest of the clock period by the RS latch. The singlebit
design uses direct-path FIR DAC to compensate for
the delay of the main FIR DAC. Thanks to single-bit operation,
the input feed-in path, compensation FIR DAC,
and summing amplifier (shown in red in Fig. 13(b)) can
be compactly integrated with the quantizer (blue), as
described below.
Fig. 13(d) shows the simplified implementation of the
colored parts of Fig. 3(b). The output of the quantizer
()v , and its delayed versions (obtained using a chain of
flip-flops), excite capacitors CC
00
aj
,, , which form the
compensation FIR DAC. The loop filter output y, and the
input u are summed with the compensation DAC using
the capacitors Cy and Cu, respectively. Cx is chosen
to be about a tenth of Cy. Capacitive summation is robust,
as the relevant coefficients are set by capacitor
ratios. It is also very compact, since small capacitors
can be used, which in turn reduce loading on the loop
filter. The attenuation caused by capacitive summation
and the parasitic input capacitance of the latch is not
of much consequence since the quantizer output only
depends on the sign of its input.3
As a result of the techniques described above, the
compensation DAC and quantizer occupy very little
space. This approach is fundamentally made possible
due to single-bit operation; a multi-bit CTΔΣM would not
benefit from this technique.
3A potential problem is the increased regeneration time of the quantizer
due to the attenuation caused by passive summation. The half-cycle
delay greatly helps in this aspect.
(a)
(b)
Main DAC
Loop filter
Flash
Clock drivers
(c)
AP-SYS2700
BPS0P080
Allen
band-pass filter
Avionics
on-board
crystal osc.
LDO
MATLAB
UART
ip
NorthHills
0311LB
im
SPI
CTDSM
LT3042
FPGA
LVDS
@ fs
6.7
9.5
multi-bit
signal
generator
24mW
5.5
2.4
0.16
17.7mW
5.8
2.7
9.0
single-bit
loop filter DACs
1.67
0.29
0.25
0.68
0.005
multi-bit single-bit
0.77
CLKgen.
ADC
Figure 14. Die micrograph. (a) Multi-bit prototype. (b) Single-bit prototype. (c) Measurement setup. (d) Area and power comparison
between multi- and single-bit designs.
THIRD QUARTER 2023
IEEE CIRCUITS AND SYSTEMS MAGAZINE
65
0.25
Comp. DAC
LVDS
SPI
(d)
MainDAC
Clock
drivers
1140um
Loop filter
QTZ +
comp. DAC
LVDS
SPI
1240um

IEEE Circuits and Systems Magazine - Q3 2023

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