IEEE Circuits and Systems Magazine - Q3 2023 - 66

We showed that the problem of flicker noise in the input integrator
can be addressed by a combination of appropriate
OTA topology and FIR feedback.
VI. Measurement Results
Prototype multi-bit and single-bit CTΔΣM chips were
fabricated in a 180 nm CMOS process. Fig. 14(a) and
(b) shows the die photographs. Fig. 14(c) shows the
measurement setup. The sine-wave input from an audio
precision (AP-SYS2700) signal generator is filtered
by a band-pass filter (Allen Avionics BPS0P080B)
and converted into differential form using a balun
(North Hills 0311LB). The output of the balun drives
the CTΔΣM input. An on-board low phase-noise crystal
oscillator (CB3LV-32/48M) serves as the master
clock. The modulator's reference voltage is supplied
by a low dropout regulator (LT3042). The high speed
CTΔΣM clock and data is brought out of the chip using
an LVDS buffer, captured on an FPGA, and processed
on a workstation.
It is interesting to compare the performance of the
multi-bit design with that of the single-bit one, and take
stock of how power and area of individual blocks compare
in the single- and multi-bit cases. Fig. 14(d) shows
this comparison. The single-bit design dissipates more
power in the loop filter, but significant savings are
achieved in the DAC (due to reduced switching power),
quantizer and clock generator, even though the clock
rate is 1.5× higher than that used in the multibit CTΔΣM.
Comparing the areas occupied by the modulators, we
see that the compensation DAC and quantizer of the
single-bit design are significantly smaller than those in
their multibit cousin. A word of caution is in order here;
the tolerance of the two designs to clock jitter is different,
with the single-bit modulator being significantly
more sensitive.
100
120
20
40
60
80
-120
-100
-80
-60
-40
Input amplitude (dBFS)
Figure 15. Measured SN(D)R as a function of input amplitude
for an 80 kHz input. (a) Multi-bit design. (b) Single-bit design.
66
IEEE CIRCUITS AND SYSTEMS MAGAZINE
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Fig. 15 shows the measured SNDR as a function of input
amplitude, for an input tone at 80 kHz. The achieved
dynamic range (DR) is about 107.5 dB in multi-bit design
and 104 dB in single-bit design. The 3 dB lower dynamic
range in the latter case is to be expected due to its lower
MSA. The kink in the SNDR plot [18] at about −40 dBFS
is due to tones caused by the DWA algorithm; at this amplitude
level, some of these tones caused by first-order
shaped mismatch noise fall into the signal band degrading
the in-band SNR. Thanks to the single-bit quantizer,
the DR curve is linear with respect to input amplitude.
VII. Conclusion
We discussed various problems encountered during
the design of high-resolution CTΔΣMs with wide bandwidth.
The linearity of the feedback DAC and flicker
noise of the loop filter turned out to be the main challenges
that need to be addressed. We discussed the
virtual-ground-switched resistor DAC and the zapped
virtual-ground switched dual RTO DAC as potential
candidates to realize the main feedback DAC in a highresolution
CTΔΣM. We showed that
the problem of
flicker noise in the input integrator can be addressed
by a combination of appropriate OTA topology and FIR
feedback. We compared the measured performance of
prototype 180 nm CMOS multi-bit and single-bit designs
targeting 17-bit resolution in a 250 kHz bandwidth.
It appears that the performance of both designs
is similar, but the area and design complexity of the
single-bit CTΔΣM is considerably smaller than that of
its multi-bit cousin.
Multi-bit
Single-bit
Multi-bit
Single-bit
Raviteja Theertham (Member, IEEE)
received the B.Tech. degree in electronics
and instrumentation engineering
from Amrita University, Bangalore,
India, in 2014. After a year in
industry, he joined the Indian Institute
of Technology Madras in 2015 and received the
M.S. and Ph.D. degrees in electrical engineering in
2021. He is currently with the Toronto Design Center
of Analog Devices Inc. He is a recipient of the Institute
Research Award from IIT Madras for excellence
in doctoral research. His current research interests
include the analysis and design of continuous-time
data converters.
THIRD QUARTER 2023
SNDR (dB)
IEEE Circuits and Systems Magazine - Q3 2023

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