IEEE Circuits and Systems Magazine - Q3 2023 - 73

Approximate and Time-Speculative Hardware
Figure 2. Prof. Sergio Bampi giving his talk in Cuenca.
Figure 3. Prof. Mounir Boukadoum giving his talk in the
CASS Tour at Guayquil.
Figure 4. Prof. Marco Lanuzza, University of Calabria, Italy.
II. The Talks of IEEE CASS Tour Ecuador 2023
The abstract of the technical talks done during the CASS
Tour Ecuador 2023 are:
Travelling Inside a Chip (by Ricardo Reis). An important
way to understand the operation of computer
and electronic circuits and systems is to analyze how
these circuits and systems are implemented. We will
take a tour inside various chips, showing solutions
from the physical level to the system level, solutions
observed through reverse engineering of microprocessors,
such as the Z8000, and that are not described in
the literature. It also shows the use of visualization to
understand how EDA algorithms and tools work for
physical synthesis.
THIRD QUARTER 2023
Design for High Performance and Energy-Efficient
CMOS Accelerators (by Sergio Bampi). Approximate
computing (AxC) is a digital design technique to improve
the performance and energy-efficiency for many
applications which inherently tolerate compute errors.
Logic design for arithmetic operator approximations
and timing-speculative (TS) hardware design techniques
were addressed in this talk. TS hardware design
paradigm allows either increasing operating frequency
or decreasing the voltage beyond the limits determined
by static timing analysis (STA), thereby narrowing pessimistic
safety margins that conventional digital design
methods usually adopt to prevent hardware timing errors.
Timing errors need to be evaluated by accurate
gate-level simulations, but a significant gap remains in
practice: How do these timing errors propagate from
the underlying accelerator hardware all the way up
to the entire algorithm behavior, where they just may
degrade the performance and quality of service of the
application at stake? This presentation demonstrated
a cross-layer framework developed at UFRGS that is
capable of performing investigations of both AxC (i.e.,
from approximate arithmetic, approximate synthesis,
or gate-level pruning) and TS hardware design (i.e.,
voltage over-scaling, frequency over-clocking, temperature
margins, and device aging). The framework
proposal can simulate both timing and logic errors at
the gate-level by crossing them dynamically, linking
the hardware result with the algorithm-level, and vice
versa during the evolution of the application runtime.
Unlike previous works, this is holistic in the consideration
of the tradeoff of AxC and TS techniques at the
application-level. This framework maximizes energy efficiency
and performance by identifying the maximum
approximation levels at the application level to fulfill
the required good enough quality. Its application was
evaluated for a few design cases in video encoding algorithms,
image processing, and in voltage over-scaled
CMOS designs.
Integrated Circuits in Ecuador (by Ramiro Taco).
Unfortunately, electrical engineering students in Ecuador
are not exposed to the design of Integrated Circuits.
Design of digital and analog circuits include labs and
exercises using discrete elements thus students are not
encouraged to use state of the art techniques or electronic
design automation tools. In this presentation, I
discussed the experience at Universidad San Francisco
to build the first modern integrated circuits thanks to
educational programs offered by IEEE. In the talk we will
discuss basic analog and digital design done by undergrad
students in the period of one semester. The talk
discussed the full custom methodology for simulation,
IEEE CIRCUITS AND SYSTEMS MAGAZINE
73
IEEE Circuits and Systems Magazine - Q3 2023

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2023
