IEEE Consumer Electronics Magazine - May 2018 - 107

using three adders and three multipliers based on the as-soon-as-possible
scheduling algorithm. Hardware allocation and binding are performed on
the scheduled DFG to design the datapath. The datapath of the proposed
obfuscated JPEG image decompression IP is designed using ten 32:1 and
two 16:1 multiplexer, five 1:32 and one
1:16 demultiplexer, 40 registers, and 18
latches. As shown in Figure 3, the
designed JPEG decompression IP core
accepts an 8 × 8 compressed image
block stored in a device (after performing run-length decoding and inverse
zigzag scanning) along with 2-D-DCT
coefficients and standard quantization
matrix and generates leveled off output
pixel intensity of the reconstructed
image [3]. Finally, the reconstructed
image pixel intensity of each block is
stored in a hardware queue and produces the decompressed image when
the processing of all compressed block

Storage

the ith 8 × 8 input image block taken
from a 512 × 512 input image matrix.
The input image block is then compressed through a JPEG compression
process as shown in Figure 4(c). JPEG
compression can be achieved through
software or hardware or a combination
of both. The quantized image after performing DCT of the input Barbara
image is shown in Figure 4(d), where
quantization is performed using quantization level 90 (Q 90) . To reconstruct the
decompressed image, dequantization is
performed on the quantized image to
generate the dequantized image shown
in Figure 4(e). Each block of dequantized image is then decompressed
through our proposed obfuscated JPEG
decompression IP core, shown in Figure 4(f), and produces 8 × 8 decompressed image blocks. The ith 8 × 8
decompressed image block is shown in
Figure 4(g). Finally, a complete 512 ×
512 decompressed image as shown in

The JPEG process that centers on the discrete cosine
transformation is one of
the most popularly used
lossy image compression
techniques in software.
is done. The proposed JPEG decompression IP core design is implemented
in Intel Quartus Cyclone II field-programmable gate array (FPGA). Each
component of the designed datapath
and controller of the JPEG decompression IP core is implemented using very
high-speed integrated circuit hardware
description language.

MOTIVATIONAL EXAMPLE
The 512 × 512 grayscale Barbara image
shown in Figure 4(a) is used for demonstration purposes. Figure 4(b) represents

Run-Length Decoding

Inverse Zigzag
Scanning of
Quantized Matrix

1-D to 2-D

Conversion

Compressed
Image Data
64
..
.
.
.
.
.
2
1
8 8 Standard
Quantization
Matrix Queue

JPEG
Decompression DFG
Obfuscation
Block

8 Compressed Block

Obfuscated
JPEG
Decompression
DFG

JPEG Decompression IP Core
Multiplication with
Quantization Matrix

HLS
Framework

Inverse Transformation
Using 2-D-DCT Coefficient
Matrix

c7
-c7
.
.
.
.
-c1

Leveling the Output
Data (+128)

o88
..
.
.
.
.
.
o12
o11

Block 1

Block 2

Block 3

Output Hardware Queue

...

2-D-DCT Coefficient
Matrix Queue
o88
..
.
.
.
.
.
o12
o11

Output Image

Pixel Intensity

Block N 2/64

FIGURE 3. The proposed hardware flow of the obfuscated JPEG decompression IP core. HLS: high-level synthesis.

may 2018

IEEE Consumer Electronics Magazine

107

Table of Contents for the Digital Edition of IEEE Consumer Electronics Magazine - May 2018