IEEE Consumer Electronics Magazine - September 2018 - 14

The target defectivity rate for
the memories must be below
1 part per million.
The target defectivity rate for the memories must be below 1
part per million (ppm). A main issue for embedded NVM is
the temperature, up to 200 °C, reached in under-the-hood
worst-case scenarios that severely threaten the storage nonvolatility. The discrimination of the stored data is achieved by comparing a physical quantity (e.g., a threshold voltage or a read
current) against a reference level that is placed between the
cells, distribution of logical "1" (i.e., the program state) and
logical "0" (i.e., the erase state).

NVM OPERATING IN HARSH ENVIRONMENTS
The application of a high temperature on the memory causes
a degradation of the physical properties of the cells, thus
shifting the distributions close to each other, with some cells
in the distribution tails erroneously crossing the read level
(causing data corruption). Typical consumer NVMs are
designed in the front end of the semiconductor process and
can operate below 125 °C, guaranteeing the data storage
for a few years at that temperature only for a very low write
cycling count (i.e., the measure of the memory lifetime wearout due to repeated data writing and erasing). Special memory designs are needed in automotive environments. The usual
design solutions incorporate single-bit-per-cell storage paradigms coupled with robust complimentary metal-oxide-
semiconductor (CMOS) technologies that are quite far from
state-of-art consumer products. In the automotive environment, care must be taken against vibrations, mechanical
stresses, and induced electromagnetic issues due to high currents flowing in some actuators, which could modify the data
retention features. NVM solutions based on electrically erasable programmable read only memories (EEPROM) were
developed in the mid 2000s to cope with temperature issues.
Multikilobyte memory modules, functionality and data
retention of over 30 years for the automotive temperature
range have been achieved by a custom cell design in a 0.35- nm
process. Write cycling of more than 200,000 writes, up to
180 °C, has been demonstrated. The drawbacks of these solutions lie in the write and erase times (i.e., a few milliseconds)
and on the limited storage density, which is critical to limit
the cost per bit. In such a landscape, NOR flash became the
de facto storage medium for code and data automotive applications. Attractive features of this technology are the lowread-access latency (hundreds of nanoseconds) and a long
endurance of the storage medium, which is diversified in
relation to the memory application that could be pure code
in-place execution or data storage [20]. Data storage NOR
flash exhibits a higher endurance (up to 500,000 write cycles)
to cope with the new requirements dictated by electronic control unit (ECU) applications like gas emission control or start/
14 IEEE Consumer Electronics Magazine

september 2018

stop commands. Among the technology variants that can be
integrated (i.e., 1T-NOR, 2T-NOR, and split-gate), the fully
Fowler-Nordheim concept stands out due to its lower energy
consumption for programming operation and easy integration
for large-density products [20]. From the pure reliability
viewpoint, the erase operation has always been an issue for
NOR flash technology so far [22]. In the last decades, special
emphasis has been put on the reduction of the erase-failure
mechanisms by implementing proper correction algorithms
or failure-screening techniques aiming at a fail-rate reduction
below 1 ppm. Such activity involves recovery algorithms that
place a burden on the erase latency, error correction codes
(ECC) design for fast error detection and correction to limit
the impact on the read latency, and redundancy-based solutions that increase the costs of the final product where the
NVM is embedded.
An additional item that arose as a limiting factor for
NVM in code/data storage for the automotive industry is
the scalability of the memory bitcells, which is a function
of the technology node used in the product integration [20].
Due to the severe constraints in terms of data retention
after storage, it is impossible to scale the dimensions below
a certain limit. Hence, classic EEPROM/flash cells cannot shrink in a cost-effective way. To this aim, innovative
memory cells, integrated in the back end of line of the
CMOS processes, are explored to overcome the scaling
barrier while improving the read/write performance of
embedded NVMs [23]. The emerging memory concepts
stem from the charge storage paradigm to interpret the
information and, therefore, are based on radically different
physical principles.
Phase-change memories are the first emerging concept
studied to replace NOR flash. Their operating principle
relies on the phase transformation of a small volume of
phase-change material (e.g., a chalcogenide compound)
between an amorphous phase (high resistivity) and a crystalline phase (low resistivity). The contrast in conductivity
between the two phases allows discrimination of the stored
information. The principal advantages of this technology are
low programming voltages, short reading/programming
times, good shrinking prospects, and low manufacturing cost
due to the reduced number of mask levels [24]. However,
there are some limiting factors in terms of data retention that
do not make this memory a good candidate for automotive
use. Materials research is being exploited to find a solution.
An interesting noncharge-based NVM concept for the automotive environment has been studied with MEMS-based
memory cells. The working principle of a single memory element is based on a teeter-totter MEMS element [25].
When applying a voltage on the pull-in electrode (program
electrode), an electrostatic force will tilt the plate to touch
the right contact electrode.
The stiction forces at this contact point will keep the floating plate in this position. While in this position, a voltage can
be applied on the left pull-in electrode (erase electrode),
resulting in an electrostatic force on the left side of the

Table of Contents for the Digital Edition of IEEE Consumer Electronics Magazine - September 2018