IEEE Consumer Electronics Magazine - September 2018 - 15

Table 4. The benchmarks of different embedded NVM technologies for automotive environment
(data from [20], [23], [25], and [26]).
NOR Flash
Data Storage

PCM

MEMS
Based

RRAM
Conductive
Bridge RAM

TAS-MRAM

Parameter

EEPROM

NOR Flash
Code Storage

Endurance

500 k

10 k-100 k

500 k-1 M

>1 M

100 k

>1 M

Data retention

>10
years/125 °C

10
years/125 °C

>10
years/125 °C

10
years/85 °C

>10
years/125 °C

10
years/85 °C

>10
years/125 °C

Power consumption

Low

High (write)

Low

High

Read latency

20-50 ns

<20 ns

>20 ns

>100 ns

>20 ns

50-100 ns

Cost per bit

Medium/
high

Medium

Low

High

Low

High

System Functionality

cost per bit are still limiting factors. Table 4 shows the paramefloating plate. When this electrostatic force reaches a threshters for each embedded NVM technology.
old value, it will overcome the stiction forces at the right contact electrode, and the plate will tilt to the left and land on the
left contact electrode. The advantages of this memory techAUTOMOTIVE MCUS AND COMPUTING PLATFORMS
nology include very good data retention at extreme temperaThe high computation needs of automated and connected
tures and a low operational power, but the overall area
cars is changing the scenario of automotive computing platoccupation of the MEMS element is still too much to be inteforms (see Figure 8). The state of art can be grouped in lowgrated in multimegabit-embedded NVMs. Recently, resistive
power MCUs, 32-bit MCUs for general-purpose operations,
random access memory (RRAM) and conductive bridge
and artificial-intelligence (AI) autonomous car platforms.
RAM gained interest as embedded products in MCUs. This
All classes support, with different security levels, cybersecutechnology uses a dielectric or a chalcogenide, which is norrity coprocessors. Low-power MCUs are used for simple
mally insulating but can be made conductive through a filacontrol and sensor or actuator interface tasks. For example,
ment or conduction path formed after the application of a
the STM8A family, in 130-nm technology, has an 8-bit Harsufficiently high voltage [24].
vard three-stage pipelined single-core architecture. It offers
Considerable progress has been made in device integration
20 MIPS at 24 MHz, a 10-bit A/D converter (ADC), two
as well as in understanding the physical/chemical properties of
comparators, a 2-128-kilobyte program NVM, 2-6-kilobyte
the resistance change behavior. Although memory arrays in the
data RAM, and several serial interfaces of up to 1 megabit/s.
literature demonstrated good performance, the intercell (varia32-b MCUs are dominating the market for active safety and
tions between cells) and intracell (cycle-to-cycle variations of
X-by-wire control tasks due to their good tradeoff between
any given cell) variability prevent RRAM manufacturing from
computational capability and functional safety, up to Autofast commercialization. Several limits appear on the temperamotive Safety Integrity Level (ASIL-D). For example, the
ture sensitivity of the storage medium.
Among magnetic RAM under testing,
thermally assisted switching is a good
candidate for harsh environments [26].
Assist ACC
Emergency
The data storage is based on the curInform
Brake Lane Self Driving
rent-induced magnetization switch of
Self Driving
Lane
Keeping
Departure Steering
magnetic materials: depending on the
Assist
Blind Spot
imposed field direction versus that of a
Parking Assist
In-Vehicle
Automotive
reference layer, a defined resistance of
Electromechanical
Infotainment
AI Computer
Safety
the material is achieved. The reliability
Airbags ABS ESC
and the cell-to-cell variability in autoSafe Driving
motive tests (i.e., 500,000 write cycles
and 200 °C data-retention targets) have
LPMCU
32-b MCU
been assessed on 1-kilobyte arrays ma10 MIPS
100 MIPS
1 GFLOPS 10 GFLOPS 100 GFLOPS 1 TFLOPS
nufactured with many back-end processes [27]. Despite the good read/write FIGURE 8. The computational needs versus autonomous/assisted-driving functions [28].
speed, power consumption and high LPMCU: low-power MCU; GFLOPS: giga-floating-point operations per second.
september 2018

IEEE Consumer Electronics Magazine

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