IEEE Consumer Electronics Magazine - September 2018 - 16

New actors are entering the
market: Nvidia and Intel, which
signed partnerships with mass
market car makers to have AI cars
on the roads by 2020.
ST SPC5 and Freescale MPC56 families include, in 90- or
40-nm technology, a feature 32-bit PowerPC instruction set,
one single or up to four cores (a dual lock-step approach), a
floating point unit, up to 8 megabytes of embedded flash
memory, a multichannel 12-bit ADC, and serial interfaces of
up to 10 megabits/s. The Infineon Aurix, integrated in 50
brand cars, ranges from a 300-MHz triple-core device with
720 MIPS and 8 megabytes of embedded flash memory
down to an 80-MHz single core with 130 MIPS and 0.5-megabyte flash memory.
In terms of ECU connectivity, the trend is to increase the
data rate using gigabits/second Ethernet. In-vehicle networks need deterministic behavior and hard real-time constraints. To this aim, the Ethernet Time Sensitive Network
initiative has been started, which ensures that all units
involved in real-time communication have a common understanding of time and adhere to the same rules in processing
and forwarding data and selecting communication paths and
in reserving bandwidth and time slots, utilizing more than
one simultaneous path to reach fault tolerance. Autonomous
cars require the whole perception process to be qualified
ASIL-D according to the ISO 26262 standard [5]. This can
be achieved by performing redundant computations with
dissimilar implementation techniques on two or more safe
high-performance computing (HPC) units, which apply parallel computing and directly access high-bandwidth sensors
(e.g., radar, lidar, and cameras) through Ethernet. Each of
these HPC units should be qualified as at least ASIL-B,
implementing safety mechanisms such as ECC in memory,
parity and/or cyclic redundancy checks in caches, and in onchip networking infrastructure. The redundant results can
then be compared by an ASIL-D safe MCU, which monitors
the computations and decides whether the results can be
trusted. The supervising MCU will be connected to the car
backbone with a run-time environment compliant classic
Autosar platform.
From a software (SW) point-of-view, implementing the
classic Autosar platform ensures the highest real-time and
safety capabilities, taking over functionalities that need
response times in the lower ns domain as well as safety monitoring capabilities in the HPC domain. Currently specified
and developed, the Autosar adaptive platform will become
the automotive standard for HPC automotive units. Since the
service-oriented network protocols are the same in the classic
and adaptive platforms, interoperability between the two is
a given. The Autosar adaptive platform defines a service16 IEEE Consumer Electronics Magazine

september 2018

oriented middleware as well as system health monitoring for
automotive HPC ECUs, which can run on POSIX PSE51compatible operating systems. Since the Autosar adaptive
platform is available on Linux, this opens the door to the
world of Linux-based infrastructure SW.
From a hardware point-of-view for the safe MCU, there
are 32-bit cores already available, such as Infineon Aurix,
that can be adopted. For the HPC units, massively parallel
platforms are appearing in the car market. Mass production
of the Renesas R-Car H3 in 16-nm nodes is expected in 2018.
The R-Car H3 includes eight 64-bit A57/A53 ARM cores
with an L1/L2 cache plus a 32-bit R7 core with an L1 cache,
offering 40,000 MIPS plus a PowerVR GX6650 graphics
processing unit (GPU) with video coprocessors (H.26x/
MPEGx codec, image recognition, and distortion compensator) and 192 ALU cores for 3-D graphics with 0.1 tera floating-point operations per second (TFLOPS) and 4K video
display/streaming. The R-Car H3 is ASIL-B with a rich set of
high-rate interfaces, including Ethernet. The power consumption is tens of watts.
To bring onboard cars TFLOPS capability and AI technologies, new actors are entering the market: Nvidia and
Intel, which signed partnerships with mass market car makers to have AI cars on the roads by 2020. At the 2017 CE
Show, Nvidia presented the Xavier AI car's computer (7 billion transistors in 16-nm technology). It has 30-TFLOPS
capability for a power consumption of 30 W thanks to eight
ARM 64-bit cores plus a 512-core Volta GPU supporting an
8K video codec as well as a computer vision accelerator.
Intel Go is a new brand for the automotive industry. A multichip platform is available using Aurix ASIL-D 32-bit MCU
enhanced by an ATOM C3000 core in 14-nm technology,
and by Arria 10 FPGA (it includes an embedded dual-core
1.5-GHz ARM A9 core, more than 1 million logic elements,
1.7 million user flip-flops, and a 1.3 TFLOPS IEEE754
floating point unit). This platform sustains L3 automation in
which the system performs the driving task but a human
driver will intervene when requested. A new Intel platform is
announced using two multichip boards, based on Xeon powerful processors, connected with 16-port 10-gigabit Ethernet
to sustain L4 high automation, in which the system can perform the driving task without human intervention, and L5
full automation, in which the system takes over all aspects of
driving full time. The power cost of HPC automotive platforms is from tens to hundreds of watts, e.g., from 30 W of a
Xavier chip to 500 W of the 320 TFLOPS Drive PX Pegasus
board. Due to the high temperature of under-the-hood car
electronics, passive cooling systems are not enough. The
design of low-cost/low-size active cooling systems for HPC
is a new challenge.
To ensure high-bandwidth wireless connectivity (e.g., for
real-time map downloading, infotainment, over-the-air SW
updates, diagnostics, and V2X), two solutions can be adopted: IEEE 802.11p [29] or Cellular-V2X. IEEE 802.11p uses
10-MHz channels within the 5.85-5.925-GHz band to
achieve data rates of several megabits/second. IEEE 802.11p

Table of Contents for the Digital Edition of IEEE Consumer Electronics Magazine - September 2018