IEEE Consumer Electronics Magazine - September/October 2019 - 49

Figure 3. Experimental results of nn corun with
SPEC CPU2006 benchmarks.

messages from CPU and the GPU cores are treated
differently. If the data block requested by the L1
cache is in the L2 cache, then the data block is
directly read and sent to the L1 cache. If the
requested data block is not in the L2 cache and
the L2 cache has free space, the data are read
from main memory and written to the L2 cache
and then the data are returned to the GPU L1
cache. If the requested data block is not in the L2
cache and there is no free space in the L2 cache,
depending on the cache sensitivity of the CPU and
GPU applications, we either allow the request to
access the L2 cache or bypass to the main memory. If the CPU application is cache insensitive, the
cache request is directly of warps currently running on the core. If the GPU application is insensitive to the cache and the warp is greater than the
Threshold_warp, the message is forwarded to the
Directory Controller for processing (see Figure 2).

CASE STUDY
The IPC of CPU applications increase through
the proposed technique (see Figure 3). We
achieve the maximum performance improvement by 53.7% and the average improvement is
15.6% compared with the classic mechanism
(LRU). As compared with the previous work
(BBR), the maximum improvement is 31.4%. The
performance of nn is improved and we can
observe a minor performance degradation in
only a few cases. Overall, the GPU application
performance is increased by up to 14.3% and
8.1% on the average compared with LRU. As
compared with BBR, the maximum improvement
is 11.3%, with an average improvement of 2.0%.
In the backprop GPU application, the IPC of
CPU applications increase with the maximum
improvement of 27.1% as compared with LRU. As

September/October 2019

Figure 4. Execution time.

compared with BBR, the maximum improvement
is 15.0%. In most cases, backprop performance has
improved, with the highest growth rate of 23.3%
as compared with LRU. As compared with BBR,
the maximum improvement is 13.0%.
Our proposed mechanism has a maximum
reduction of 43.5% as compared with LRU (see
Figure 4). As compared with BBR, the maximum
reduction is 25.1%. Our proposed mechanism
only increased by 0.9% on average in power consumption and, hence, the overhead is very low.
The implementation overhead of our proposed
technique includes control logics and storages
to save CPU/GPU states.

CONCLUSION
This paper presented a bypassing-basedshared cache management mechanism. It considered the current memory access characteristics of CPU and GPU applications when selecting
Bypass, so as to determine whether the GPU
application needs to access the memory without
accessing the shared cache. In heterogeneous
multicore architectures, optimized cache replacement mechanism can bring benefits to the CE
system performance.

ACKNOWLEDGMENTS
This work was supported by the Beijing Natural
Science Foundation under Grant 4192007.

& REFERENCES
1. J. Brandenburg and B. Stabernack, "Simulation-based
HW/SW co-exploration of the concurrent execution of
HEVC intra encoding algorithms for heterogeneous
multi-core architectures," J. Syst. Archit., vol. 77,
pp. 26-42, Jun. 2017.

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