IEEE Consumer Electronics Magazine - March/April 2020 - 67

Column: The Art of Storage

New Electronic
Architectures
Tom Coughlin
Coughlin Associates

Abstract-With the slowing of traditional semiconductor scaling, specialized processors,
packaging and communication between chips has assumed increasing importance in
meeting the needs of big data, IoT, and AI markets that will explode in the 2020 decade.
Semiconductor designers are looking for new ways to provide the increasing computing
capability needed to support our data intensive future. This led to multicore processors,
processor accelerators, and the concept of chiplets and high-density interconnects.

& KEY

characterize many high
current package designs are a move toward
greater package-level integration and SoC disaggregation.1 The important technology developments on packaging are thin/small footprint
client product packages (e.g., smart phones and
wearables), powerful delivery architectures,
control of heat production even with high-speed
signaling, density and pitch scaling for chip
interconnects, and design with heterogenous
devices from multiple sources.
In addition to smaller area for integrated electronics, the packaging is getting thinner, often by
thinning and stacking die and by building some
structures on the back of the die. Performance
options are also increasing. Bandwidth density
FEATURES THAT

Digital Object Identifier 10.1109/MCE.2019.2954255
Date of current version 7 February 2020.

March/April 2020

is a product of the wire data rate times that is
called the wiring density (# of IO/mm) and is
expressed in GBps/mm. Figure 1 shows the bandwidth density for several types of devices, particularly memory devices.2
Putting processing closer to memory is a very
important element to improve the performance,
especially latency and also for improving power
efficiency, since much power is used to move
data to processing to memory and back. The use
of high bandwidth, low-power dense parallel
links [such as high bandwidth memory (HBM)]
is driving the need for high density die-to-die
interconnects.
Intel and Advanced Micro Devices (AMD) are
both using chiplets in their next generation servers. In this approach, monolithic processors are
broken into smaller specialized chips, called chiplets. These chiplets are connected together on a
multichip module (MCM). Using this architecture,

Published by the IEEE Consumer Electronics Society

2162-2248 ß 2019 IEEE

67



IEEE Consumer Electronics Magazine - March/April 2020

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