IEEE Consumer Electronics Magazine - November/December 2020 - 74

Consumer Electronics Security

Figure 1. Different stages of the IC supply chain where many of the untrustworthy parties involved receive a
complete white-box accessibility to the design. Hence, malicious modifications of the IC design could be
made at any stage before fabrication. Modification could also be done even at the board level during system
assembly.

supply chain to be potential adversaries. Finally,
we identify possible avenues for future research
by discussing a scenario where most of the existing mechanisms no longer apply.

MICROELECTRONICS TRUST
Semiconductor Supply Chain and Associated
Trust Issues
In this section, we describe the various steps
involved in manufacturing a digital IC using
Figure 1. This flow is partially applicable to other
forms of microelectronics, such as analog,
optoelectronic, microwave, and discrete components. However, existing research on microelectronic trust has heavily focused on digital ICs.
We highlight the role of third-party vendors in
each step and the potential avenues available
for injecting hardware Trojans.
Integrity of Behavioral Models: The economic
benefit obtained from a shorter design cycle and
reduced development cost has driven the semiconductor industry toward a third-party IP
(3PIP) based ecosystem. Hence, depending on
the specification, the design house may purchase 3PIP cores in the form of register-transferlevel (RTL) codes or gate-level netlist from various other IP vendors and integrate into their
design. For instance, apart from the dual-core
central processing unit, the Apple A9 system-onchip (SoC) present in many Apple products contains the PowerVR GT7600 graphics processing
unit from Imagination Technologies.4 If a 3PIP
vendor has any dishonest intent, they can insert
malicious circuits into their IPs to facilitate that.
Hence, an essential step in incorporating these
cores into the SoC design is to verify their integrity. Trust verification is a laborious task compared to functional verification as the designer
has no knowledge of the internal implementation

and has to rely only on the specification of the
design. Additionally, the verification step has a
specified time budget due to the time-to-market
requirement.
Trusted Synthesis: The RTL design is converted to its gate-level representation using commercial electronic design automation (EDA)
tools. The subsequent conversion of the gatelevel design to layout also requires extensive use
of various EDA tools that are almost always developed by third-parties. The designers observe
these EDA tools as black-box and, consequently,
the integration of hidden functionality by the
software during the synthesis process could go
undetected.5 A rogue employee within the design
house could also incorporate such malicious circuitry. Therefore, even the trusted in-house IPs
are vulnerable to malicious alterations by thirdparty EDA tools and corrupt workers.
An RTL design could occupy only a few hundred to a few thousand lines of code, and the corresponding gate-level netlist could potentially
span thousands to million gates, thus increasing
the attack surface for the third-party entity as the
design progresses further in the manufacturing
process. Additionally, unlike functional constraints, there are no golden references for quality
constraints such as delay, power, and area. Thus,
the attacker is no longer constrained by these criteria while designing a complicated triggering
mechanism to bypass an accidental activation.
Besides, the attacker could inject backdoors into
the design that might not affect the functionality
of the design but could compromise the quality
parameters. Hence robust verification techniques
are required that quantify the integrity of the
design from a parametric perspective in addition
to the functional correctness within a given time
constraint. Additionally, the cost of changing the
design increases as we progress further into the

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