IEEE Consumer Electronics Magazine - November/December 2021 - 56

Column: The Art of Storage
Future Images with Future
Memory
Tom Coughlin
Coughlin Associates
& EMERGING NON-VOLATILE MEMORIES, such as
resistive random access memory (RRAM) and
magnetic RAM (MRAM) can scale smaller than
NOR flash in embedded devices and is replacing
NOR used for code storage for devices with
less than 28nm feature sizes. In addition,
MRAM, with performance as good as higherlevel
SRAM cache and with a cell size much
smaller than SRAM with its 6 transistors allows
creating more memory capacity in a smaller
space than SRAM.
This MRAM AI cache memory is showing up
in embedded consumer devices for storing
large machine learning models for local AI inference,
such as the Ambiq Apollo4 MCU discussed
in earlier columns1,2. At a recent TSMC
Symposium the company said that 22nm MRAM
powered devices, such as Ambiq's Apollo4 are
in production for used in consumer and other
devices3.
In addition to providing more memory in the
same amount of semiconductor die, MRAM (and
RRAM) are also non-volatile and enable more
sleep states for embedded devices running on
restricted power sources such as battery
Digital Object Identifier 10.1109/MCE.2021.3095049
Date ofpublication 8 July 2021; date ofcurrent version
6 October 2021.
powered mobile devices and IoT devices using
energy harvesting. Thus, these non-volatile
memories provide ways to enable more features
and more intelligence at the network edge or in
endpoint devices, while using less power. This is
an important factor that will enable more consumer
applications.
At the 2021 IEEE VLSI conference Sony discussed
the use of STT-MRAM as a buffer memory
for 3D stacked CMOS Image Sensors
(CIS)4.AsFigure1 showsanMRAMmemory
can designed to retain data on its cells for
many years (which allows replacing eFlash
memory), or trade-offs can be made providing
more MRAM storage capacity or faster writing
speed but much lower cell data retention (but
still much higher retention than SRAM or
DRAM).
Sony chose to use low retention 40nm STTMRAM
for a memory buffer in a 3D stacked CIS
device (where multiple chips are stacked and
connected together). The MRAM bit cell size was
0.061 mm2 with a write speed of 40ns. The memory
capacity was 30Mbit with an endurance of
>1E10 cycles and 1 second retention at 85C. In
the stacked devices the perpendicular magnetic
tunnel junction (MTJ) of the MRAM device was
embedded between the contact layer and the
first metal layer.
56
2162-2248 ß 2021 IEEE
Published by the IEEE Consumer Technology Society
IEEE Consumer Electronics Magazine

IEEE Consumer Electronics Magazine - November/December 2021

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