IEEE Consumer Electronics Magazine - January/February 2022 - 58

Special Section on Security and Sustainability Technologies for Smart Cities
Figure 1. Adiabatic logic is a potential solution to security and energy needs.
for malicious cyberattacks are rapidly expanding.3
Many of these devices communicate and
store information and thus are targets for sidechannel
attacks. Side-channel attacks come in
many forms, they can exploit power consumption,4
timing,5
etc. Side-channel attacks are a
dangerous threat to consumers' personal information,
device reliability, and general well-being.
As the smart consumer electronics paradigm
emerges, there are challenging requirements to
design energy-efficient and secure systems.
Novel computing paradigms such as adiabatic
logic are promising to develop low energy
and correlation power analysis (CPA) resistant
circuits.6 Adiabatic logic recycles energy to
reduce power7 (see Figure 1). Figure 1 illustrates
adiabatic logic as a solution to both energy constraints
and security concerns. Furthermore,
adiabatic circuits can be designed such that
their evaluation networks are balanced and
therefore having equal discharge to prevent
information leakage. Many adiabatic families
operate on a four-phase clocking scheme which
can lead to high amounts of area overhead from
both interconnection routing and the clock
structure. Thus, in this article, we explore twophase
clocking to reduce area while remaining
energy-efficient and secure .
Previously, we proposed a CPA resistant adiabatic
logic family known as Energy Efficient
Secure Positive Feedback Adiabatic Logic (EESPFAL).6
EE-SPFAL operates using a four-phase
trapezoidal clocking scheme. To remain CPA
58
resistant, EE-SPFAL requires four separate
clocks and four separate discharge signals. A
large amount of interconnects can lead to large
areas on post-layout chip designs. Four-phase
clocking design can also be more complex than
their two-phase counterpart. Thus, in this article,
we propose 2-EE-SPFAL, a two-phase implementation
of EE-SPFAL to reduce interconnect
area and clock design complexity. In our 2-EESPFAL
design, we implement the circuit using a
sinusoidal wave. To demonstrate energy savings
and security, we have constructed one round of
PRESENT-80 using both CMOS and 2-EE-SPFAL.
From 100 kHz to 25 MHz, our results show an
average energy saving of 76.5% to 21.3% between
CMOS and 2-EE-SPFAL with clock generator
implemented. To demonstrate secure operations,
we also performed a CPA attack on PRESENT.
We show that we were able to retrieve the
key of the CMOS implementation of PRESENT
using 5120 traces. However, we were not able to
retrieve the key to the 2-EE-SPFAL sinusoidal
wave implementation of PRESENT-80.
BACKGROUND ON ADIABATIC
LOGIC AND CPA
Adiabatic logic is one of the low-power design
techniques for designing ultralow-energy
circuits.8 Adiabatic logic reduces the overall
energy consumed by the circuit by efficiently
recycling the energy stored in the load capacitor
after each clock cycle. The recovered energy is
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