IEEE Consumer Electronics Magazine - January/February 2022 - 59

Figure 3. Abstract illustration of CPA.
Figure 2. General structure of adiabatic logic
circuits.
then reused in the next cycle. The energy dissipated
in an adiabatic circuit is given by
Ediss ¼
RC
T
CV2
dd
(1)
where T is the charging period of the capacitor,
C is the output load capacitor, Vdd is the full
swing of the two-phase power clock (e.g., the
max of the sinusoidal waveform to ground). If
the charging time T> 2RC, then the energy dissipated
by an adiabatic circuit is less than a conventional
CMOS circuit. Figure 2 illustrates an
adiabatic circuit structure and its discharge and
recovery.
Side-channel attacks come in many forms,
they can exploit power consumption,4 timing,5
etc. Of the power analysis attacks, the CPA
attack is widely used because of its robustness
toward both symmetric and nonsymmetric cryptographic
algorithms.9 CPA attacks look to
retrieve otherwise hidden keys by correlating
the power of a circuit with a circuit's input.
CPA attacks can be conceptualized by examining
Figure 3. Without examining the blocks,
one can determine which weight is heavier by
looking at the direction of the seesaw. This is
similar to examining the power consumption to
determine the inputs without actually looking at
the inputs. If we instead balance the weights, the
seesaw remains stable and thus we cannot determine
anything about the blocks, the same can be
said if a circuits power consumption is uniform.
Similarly, depending on the input of the CMOS
circuit a different amount of power is consumed.
With this information, an attacker can correlate
January/February 2022
the power of a cryptographic circuit with the
input key. To combat this, we look to design our
circuits such that the outputs are balanced thus
the power consumption is balanced. Uniform
power consumption can be examined in Figure 4.
Uniform power consumption prevents information
leakage and thus keeps a cryptographic circuit
secure.
2-EE-SPFAL: PROPOSED TWO-PHASE
ENERGY EFFICIENT SECURE
POSITIVE FEEDBACK LOGIC
EE-SPFAL is a recently proposed low energy
and CPA resistant logic family.6 Figure 5 shows
the general structure of a 2-EE-SPFAL adiabatic
circuit. The structure consists of two balanced
evaluation networks. The structure also consists
of cross-coupled inverters acting as a senseamplifier.
Finally, the discharge transistors are used to
reset the output so that the power consumption
remains uniform. EE-SPFAL was originally constructed
with a four-phase trapezoidal clocking
scheme. In this article, we present the two-phase
design of EE-SPFAL using sinusoidal power
clocks. For two-phase EE-SPFAL to work properly
and be CPA resistant, adjustments are made to
the clocking scheme and discharge signals.
Figure 4. Uniform current consumption of the 2-EESPFAL
XOR gate.
59
IEEE Consumer Electronics Magazine - January/February 2022

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