IEEE Consumer Electronics Magazine - January/February 2022 - 60

Special Section on Security and Sustainability Technologies for Smart Cities
Figure 7. Design of four buffers using four-phase
clocking and two-phase clocking. (a) Four buffers
implemented in four-phase adiabatic logic. (b) Four
buffers implemented in two-phase adiabatic logic.
Figure 5. General structure of 2-EE-SPFAL circuit.
Figure 6 shows the proposed sinusoidal
clocking scheme. It consists of two sinusoidal
waves 180 out of phase. The clocking scheme
consists of an " evaluate " phase in which the
power clock is rising and a " recover " phase in
which the power clock is falling. There are two
discharge signals, one for each clock. The period
and delay of the discharge signals are equal to
their respective clocks.
Using two clocks rather than four results in
multiple benefits. Namely, two clocks reduce the
amount of area and complexity required to generate
the power clock. Take the four-phase clock
generator given by Hu et al.10 and the two-phase
clock generator given by Athas et al.11 as a case
study. The four-phase design consumes a
substantial area and requires a more complex
design than in the two-phase design.
The four-phase clocking scheme also leads to
a more complicated routing scheme. Using fourphases
requires four separate interconnects
when four or more gates are cascaded. Take the
four buffers seen in Figure 7(a) as a case study,
in the four-phase case, eight separate interconnects
are required for the circuit to operate correctly
while in the two-phase case only four
interconnects are needed.
TWO-PHASE ADIABATIC POWER
CLOCK GENERATOR (PCG)
This section discusses the energy-efficient
Figure 6. Proposed two-phase sinusoidal clocking
scheme for 2-EE-SPFAL.
60
adiabatic PCG which is used to operate 2-EESPFAL.
The PCG uses an external inductor and
the load of the adiabatic circuit to generate the
waveforms. There are many existing clock generators,
for this case study, we have used the
2N-2P synchronous clock generator discussed
by Mahmoodi-Meimand and Afzali-Kusha.12 The
timing diagram of the controlling external signals
is shown in Figure 8. From Figure 8, we
developed the novel way for discharge and
discharge signals to have dual-function: first, control
signals for the clock generator, and second,
discharge control for the adiabatic logic circuit.
The proposed dual-function reduces the number
of external signals necessary for operation.
IEEE Consumer Electronics Magazine

IEEE Consumer Electronics Magazine - January/February 2022

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