IEEE Consumer Electronics Magazine - January/February 2022 - 61

Figure 8. Synchronous 2N-2P two-phase clock
supporting control signals.
DEMONSTRATION OF 2-EE-SPFAL
SECURITY AND ENERGY EFFICIENCY
Each 2-EE-SPFAL gate results in a half-cycle
delay. Thus, additional buffers are inserted in
2-EE-SPFAL circuits to synchronize the outputs.
We evaluate two criteria to determine the
energy efficiency and security of 2-EE-SPFAL. The
criteria normalized energy deviation (NED) is
defined as (Emax - Emin)/Emax. NED is used to indicate
the percent difference between the minimum
and maximum energy consumption of the
possible input transitions. A second parameter,
normalized standard deviation (NSD), is defined
as se
E where se is the standard deviation of the
energy dissipated by the circuit per input transition
and E is the average energy dissipation.
Both NED and NSD are important parameters
when determining circuit resilience to CPA
attacks. NED and NSD values reported in this article
are calculated with the integration of the PCG.
Table 1 shows the simulated and calculated
parameters for the 2-EE-SPFAL sinusoidal based
NAND and XOR implementation at 12.5 MHz
with the integrated clock generator. The low
NED and NSD calculations show that 2-EE-SPFAL
Table 1. Simulation and calculation results for NAND
and XOR gates.
Parameter 2-EE-SPFAL (NAND) 2-EE-SPFAL (XOR)
EminðfJÞ
EmaxðfJÞ
EavgðfJÞ
NED (%)
NSD (%)
2.94
3.02
2.99
2.6
0.75
2.86
2.87
2.87
0.21
0.08
Figure 9. Relationship between NED/NSD,
frequency, and load for 2-EE-SPFAL XOR/XNOR
gate. (a) NED/NSD versus frequency of 2-EE-SPFAL
XNOR/XOR gate. (b) NED/NSD versus load of 2-EESPFAL
XNOR/XOR gate.
sinusoidal has minimal energy consumption
changes between the input transitions. From
Table 1, it can also be seen that the XOR gate of
2-EE-SPFAL sinusoidal has lower values of NED
and NSD compared to the NAND gate.
From Figure 4, we can observe that regardless
of input combination, the current consumption
of the XOR gate is nearly constant. The
small variations in current results in minimal
NED and NSD values and thus are theoretically
more resistant to CPA attacks.
Furthermore, we examined the relationship
between NED/NSD, frequency, and output load values.
The relationships can be seen in Figure 9(a)
and (b). We can observe that as frequency
increases NED/NSD values also increase. The same
relationship can be seen between NED/NSD and
load. As the output load surpasses 60 fF the
NED/NSDvalues begin to increase.When designing
circuits one should take into consideration these
relationships to prevent information leakage.
January/February 2022
61

IEEE Consumer Electronics Magazine - January/February 2022

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