IEEE Consumer Electronics Magazine - January/February 2022 - 83

Table 1. Performance and energy efficiency when using GPU and hybrid CPU-FPGA device to implement PHFs.
ASIC and FPGA
In the early age of password recovery, ASICbased
accelerators are the most powerful solutions.
In 1998, the Electronic Frontier Foundation
built a custom DES-cracker called " Deep Crack "
that could find a DES key in about two days.5
This machine contains over 1800 custom chips
and costs about 250 000 US dollars. However,
the huge nonrecurring engineering cost of ASIC
chips hinders its application to run the fastchanging
algorithms.
Compared with ASICs, the most distinctively
important feature of field-programmable gate
array (FPGA) is its configurability. An FPGA is
able to change its functionality to switch different
algorithms, which significantly reduces the
development time and cost of password recovery
accelerators. The COPACOBANA machine
built in 2006 consists of 120 Xilinx Spartan-3 1000
FPGAs and only costs 10 000 US dollars,6 with a
DES key being cracked in under 6.4 days on average.
This design is also suitable for algorithms
that are parallelizable and have a low communication
overhead, such as RSA and ECC.
GPU
Ever since general-purpose computing on
graphics processing units (GPGPU) was demonstrated,
GPU has been applied to areas beyond
its originally purposed graphic processing. With
a large number of processing cores inside, a
typical GPU can execute thousands of computing
tasks concurrently, which makes it a suitable
platform for password recovery. However,
the GPU's high performance comes with a high
cost in power consumption. Many studies have
shown that GPU-based password recovery
accelerators cost 2 more energy than their
FPGA-based counterparts2. The main reason is
that GPUs are not designed with this specific
January/February 2022
application of password recovery in mind.
Rather, GPUs typically contain a large number
of float-point units and special function units,
which are not appreciated in cryptographic
algorithms.
Hybrid CPU-FPGA Device
The idea of a hybrid CPU-FPGA device is to
integrate the CPU and the FPGA on the same
chip and connect them with high-speed interconnections.
There are some mature products,
such as the Zynq-7000 SoC series from Xilinx and
Stratix 10 SoC series from Intel. Figure 2 shows a
simplified model of the Zynq architecture. Its
processing system is a dual-core ARM Cortex-A9
CPU, which supports software routines and
operating systems. The programmable logic of
Zynq is equivalent to that of an FPGA, which is
ideal for implementing high-speed logic. The
advantage of a hybrid CPU-FPGA device over a
discrete CPU-FPGA combination is that the CPU
and the FPGA are tightly coupled, which means
that CPU can efficiently cooperate with the
FPGA. The smaller number of components and
the lower communication overhead also make
hybrid CPU-FPGA devices more energy efficient.
Table 1 compares the GPU and the hybrid
CPU-FPGA device in their performance and
energy efficiency. Even if the technology is one
generation behind, hybrid CPU-FPGA devices
show remarkable energy efficiency compared
with GPUs.
Figure 2. Simplified model of the Zynq architecture.
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IEEE Consumer Electronics Magazine - January/February 2022

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