IEEE Consumer Electronics Magazine - January/February 2022 - 86

Special Section on Secure and High-Speed Electronic Systems
varies for different passwords. Usually, a longer
password will need more hash computation,
which means its data need to go through the
pipeline more times. Such inconsistency will lead
to a complicated schedule unit design of the pipeline.
This problem can be solved by applying the
spatial-temporal multiplexing technique proposed
by Zhang and Liu8, which leverages the
configurability of the hybrid-CPU-FPGA device.
For each password length, the architecture of the
accelerator is customized and a new bitstream is
generated. The CPU then groups the passwords
with the same length together and configures the
FPGA with the corresponding bitstream. With this
technique, the scheduling unit of the pipeline in
each bitstream would be simplified.
Summary
Password recovery has long been recognized
as one application that needs tremendous
computing power. As so, various fast and efficient
accelerators have been proposed in the
literature.
Among many password recovery platforms,
ASICs and FPGAs suffer from high design cost
and poor flexibility and GPUs are found not
energy efficient enough due to its nature to support
general-purpose computing. The emerging
hybrid CPU-FPGA device provides both flexibility
and energy efficiency, showing a promising
application prospect. In addition, there have
also been many novel techniques proposed for
the efficient design of the CPU-FPGA-based
accelerator.
Besides hardware platforms and applicable
acceleration techniques, password guessing is
still needed to reduce the number of attempts in
the brute-force attack. Combining password
guessing methods, such as the rule-based
method, Markov model, PCFG, and PassGAN, in
password recovery could achieve a better password
guessing accuracy.
With the emergence of new password encryption
algorithms, a suitable accelerator architecture
must account for both flexibility and
efficiency. Therefore, future password recovery
systems will more than likely choose the hybrid
CPU-FPGA device for this niche application.
86
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https://tches.iacr.org/index.php/TCHES/article/view/8675 https://tches.iacr.org/index.php/TCHES/article/view/8675 https://www.github.com/magnumripper/JohnTheRipper/tree/bleeding-jumbo/src/z%tex/fpga-sha256crypt https://www.github.com/magnumripper/JohnTheRipper/tree/bleeding-jumbo/src/z%tex/fpga-sha256crypt https://www.github.com/magnumripper/JohnTheRipper/tree/bleeding-jumbo/src/z%tex/fpga-sha256crypt

IEEE Consumer Electronics Magazine - January/February 2022

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