IEEE Consumer Electronics Magazine - January/February 2022 - 90

Special Section on Secure and High-Speed Electronic Systems
Figure 2. General schematic of EE-SPFAL.7
PROPOSED DESIGNS
EE-SPFAL7 is an adiabatic logic family,
which is suitable to design low-power and
secure adiabatic circuit. EE-SPFAL has uniform
power consumption and is secure against DPAbased
attacks. A general schematic of EESPFAL
is shown in Figure 2, the block F and
block F generate the Output and Output,
respectively. More detailed background on adiabatic
logic is available in a recent article.6 We
propose two versions of the EE-SPFAL-based
adiabatic approximate adder (AAA). The function
blocks that produce Output and Output
are block F and block F, respectively (see
Figure 2). Therefore, to minimize the total size
and decrease power and energy consumption,
the two proposed adders use the complementary
output to approximate sum or carry-out
outputs. Hence, the two approximate adders
namely the TSAA based on (1) and TCAA based
on (2) are developed
F
F
¼ Sum
F ¼ Sum ¼ Cout
¼ Cout
F ¼ Cout ¼ Sum:
(1)
(2)
True Sum Approximate Adder (TSAA)
The schematic of TSAA based on EE-SPFAL is
shown in Figure 3, where Cout is the Sum complement.
We have used the dual-rail property of
the adiabatic logic to develop Cout as the complement
of the Sum (3). We, therefore, removed
the need for a separate circuit to compute Cout
and Cout
SumTSAA ¼ ABC
CoutTSAA
¼ SumTSAA
:
(3)
Figure 4. EE-SPFAL-based TCAA.
90
IEEE Consumer Electronics Magazine
Figure 3. EE-SPFAL-based TSAA.
True Carry-out Approximate Adder (TCAA)
The schematic of TCAA based on EE-SPFAL is
shown in Figure 4. In TCAA, the SumTSAA is computed
as CoutTCAA (4). We, therefore, removed
the need for a separate circuit to generate the
Sum output
CoutTCAA
¼ B CþA CþA B
SumTCAA
¼ CoutTCAA
:
(4)
SIMULATION RESULTS
AND DISCUSSION
For comparison purposes, this section uses
EE-SPFAL-based TSAA and TCAA, CMOS-based
accurate mirror adder (AMA)8 and CMOS-based
approximate mirror adders.9 The proposed
designs are evaluated in terms of power, energy,
area, and security against DPA attack. The simulations
are performed with 45-nm technology.

IEEE Consumer Electronics Magazine - January/February 2022

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