IEEE Consumer Electronics Magazine - May/June 2022 - 88

Special Section on ISVLSI-2020
& BIG DATA CENTERS require an acceptable level
of computing power, network, and storage to
provide their services. We want to look at ways
for modern data centers to increase their computing
performance to an acceptable level, using
specific hardware accelerators1 (see Figure 1).
Among the various data processing tasks of
these applications, sorting is one of the most
important.2,3 Various applications such as realtime
schedulers,4,5 searching,6,7 robotics,8,9
video and image processing,10 artificial intelligence
(AI),11,12 and multimedia systems13,14 use
sorting methods in their structures. Finding
high-performance and low-cost hardware-based
approaches to sort big data is a hot topic for
many research communities.
Hardware-based sorters utilize techniques
including parallelism, pipelining, and other special
acceleration methods to increase the
efficiency of sorters. However, no particular technique
can be considered as a general approach
that produces the desired result for each dataset.
The important note in the hardware-based sorters
is that the parallelism technique increases
the need for hardware resources, memory
resources, and power consumption that is unacceptable
in many applications.15
Many applications use field-programmable
gate arrays (FPGAs) as hardware accelerators to
accelerate some parts of their operational procedure.
In several cases, these FPGAs need to sort
some kind of data too. However, due to the limited
amount of available resources in the FPGA,
the sorting task cannot be done, because most of
the proposed hardware-based sorters need many
resources. For example, in data compression using
the Burrows-Wheeler transformmethod,16 asorter
is implemented along with other components of
the system on an FPGA chip. The limited resources
of the FPGAmay cause serious challenges in implementing
the sorting task. Therefore, it is crucial
to provide a hardware-based sorter with few
hardware resources and a desirable performance.
To this end, we proposed a three-dimensional
(3-D) hardware sorting method, the socalled
3D-Sorter, in the work by Norollah et al.17
which reduces the required resources and
power consumption noticeably. Our proposed
3D-Sorter utilized several parallel sorting units
88
Figure 1. Sorting is an essential and important
computing process in data centers.
that could sort input data in 27 phases in the
form of 3-D matrix. This article utilizes the proposed
3D-Sorter17 as a basic platform to introduce
an ultralow-power 3-D hardware sorter
(ULP-Sorter) that reduces needed resources and
power dissipation more efficiently than proposed
3D-Sorter17 and previous state-of-the-art
techniques. ULP-Sorter utilizes multidimensional
sorting algorithm (MDSA) to sort any sequence
of input records. It has also the ability to find the
largest/smallest records with a significant small
delay. Results show that ULP-Sorter reduces
number of look-up tables (LUTs) and power
consumption noticeably in comparison to previous
state-of-the-art techniques including the
basic 3D-Sorter. ULP-Sorter is the extended
architecture of 3D-Sorter that has the following
contributions.
1) Ability to maintain the performance at an
acceptable level (though, the performance
level is decreased in comparison with the
basic 3D-Sorter) while consuming lower FPGA
resources as compared to other sorting methods,
especially the basic 3D-Sorter.17 To this
end, ULP-Sorter utilizes pipelining and paralleling
techniques to achieve the goal.
2) Ability to sort 2p input records independently
via the coarse-grained bitonic sorting
and pipeline techniques, which increases the
performance.
3) Ability to find the smallest and largest input
record in the shortest time possible.
4) Ability to reduce the power dissipation to a
significant level as it utilizes the required
resources at least by half in comparison to the
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