IEEE Consumer Electronics Magazine - May/June 2022 - 90

Special Section on ISVLSI-2020
Figure 3. The procedure of switching between
different dimensions (I, J, and K) of a matrix: (a)
sorting in dimension K, (b) sorting in dimension J,
and (c) sorting in dimension I.
signal is set to zero, the smaller and larger
records are appeared on the X and Y output
lines, respectively; otherwise, the larger and
smaller records are sent to the X and Y output
lines, respectively.
Structure of Dual-Mode Pipeline Sorting
Network (DPSN)
The structures of a bitonic sorting network
(BSN) and an odd-even sorting network (OESN)
are shown in the top and bottom of Figure 2(b),
respectively. To sort four input records, BSN
and OESN require six and five CAS cells, respectively.
In our previous work (RTHS), BSN is used
as a basic building block; whereas OESN is utilized
in ULP-Sorter to reduce number of required
resources. The architecture of DPSN is shown in
Figure 2(c) that sorts four W-bit data-width input
records. The architecture of DPSN is based on
OESN and is designed with a pipeline technique.
DPSN includes a three-stage pipeline and at each
clock cycle, a new sequence of input records is
given to it for sorting. Based on the " Direction "
signal, the output can be managed in either
descending or ascending orders.
Structure of a Switch
The switch unit is the most important part of
a ULP-Sorter. This unit returns the output
records of DPSNs to the input lines of DPSNs for
the next clock cycle according to the structure
of MDSA.
Let us discuss the structure of a 3-D switch.
Figure 3(a)-(c) illustrates the procedure of
switching process between K, J, and I dimensions
as stated in the phases of 3D-MDSA. The
pseudocode of a 3-D switch is shown in
Algorithm 1. We have three types of switch
modes: 1) I to K, 2) K to J, and 3) J to I. The 3-D
matrix rotates from one dimension to another in
each switching mode. The " ctrl_switch " signal is
90
Figure 4. ULP-Sorter design to sort records of a 4
4 4 matrix.
generated by the control unit to determine the
switching mode according to the procedure of
3D-MDSA. As stated in pseudocode of Algorithm
1, each element of the output matrix is obtained
by a 4:1 multiplexer.
Algorithm 1. Pseudocode of 3-D Switch
Description
1:
2:
3:
4:
5:
6:
7:
8:
10:
11:
12:
13:
Input: 3-D matrix of (W-1) bit input records
and " N " is number of records in each dimension
of matrix
Output: Rotated 3-D matrix of (W-1) bit
records
for all K< N
for all J< N
for all I< N
case(switch mode)
J to I: output½K½J½I¼ input½K½I½J;
I to K: output½K½J½I¼ input½I½K½J;
9: K to J: output½K½J½I¼ input½N I 1½N
J 1½K;
default: output½K½J½I¼ input½K½J½I;
end case
end for
end for
14: end for
Main Architecture
The 3D-Sorter design17 uses 16 DPSN units to
work in parallel and improve the performance.
Since our main goal is to reduce the resource
consumption, we introduce a new architecture
that uses only four DPSN units to design an ultralow-power
3D-Sorter.
The architecture of ULP-Sorter is illustrated
in Figure 4 that contains a 3-D switch, two blocks
of registers to sort records, a control unit, and
four DPSN components, each with four input
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