IEEE Consumer Electronics Magazine - May/June 2022 - 91

Figure 5. Sorting process in package with three
steps.
records. Each registers block contains 64 registers
of ðW 1Þ data-width. The first register
block, like the registers used in 3D-Sorter,
receives input records from BRAMs and determines
the input of DPSNs. The second register
block has the duty of receiving output records of
DPSNs during four clock cycles (one 3-D matrix
of records) and sends them to the 3-D switch.
The control unit is more complicated than one
used in 3D-Sorter and generates five control signals,
as follows.
1) The " Ctrl_input " signal: This signal connected
to the selectors of 4:1 multiplexers,
which allows four DPSNs to receive input
records of one page of 3-D matrix at each
clock cycle.
2) The " Ctrl_output " signal: It works similar to
the previous signal in the output of DPSNs. It
is used due to the time difference between
the input and output of each DPSN caused by
the pipeline stages. It is connected to the
selectors of 4:1 de-multiplexers that store
each sorted records of pages in register
block 2.
3) The " Ctrl_switch " signal: If its value is " 11, "
the switch latches the output. Otherwise,
this signal determines the switch type.
4) The " Direction " signal: This signal determines
the sorting type.
5) The " Ready " signal: If this signal is asserted,
the records of the 3-D matrix are sorted, and
then stored in BRAMs. The host system can
read data.
By asserting the " Start " signal, 64 records are
sent from BRAMS to the internal registers. The
records form a 3-D matrix according to Figure 3
(a). The 3-D matrix does not need to be rotated
from I toKdimension in the first phase of MDSA.
After that, the " Start " signal is asserted by the
host for four clock cycles and the sorter receives
the input records from BRAMs and stores them
May/June 2022
Sorting Package
The DPSN unit with four pipeline stages can
load four input records per clock cycle; therefore,
in the first four clock cycles all input
records of " block register 1 " are loaded and after
four clocks, the sorted records are transferred
to the " block register 2. " But until all records are
sorted, the 3-D switch circuit is not being able to
work, and on the other hand, DPSN units have
four stall clocks. To increase the performance,
another p record array can be loaded and sorted
during the stall clocks. Therefore, the ULP-Sorter
can sort 2p records, independently.
91
in register block 1. In the next clock cycle, the
records of each page of the 3-D matrix enter into
DPSNs according to the 3D-MDSA algorithm and
its phases. The " Ctrl_input " and " Ctrl_output "
signals allow each of 3-D matrix pages to be
arranged by DPSNs and are stored in register
block 2, in four clock cycles. During these steps,
the " Crtl_switch " signal set to " 11, " so that the
records within register block 1 do not change. In
the next clock cycle, the 3-D matrix of sorted
records register block 2 is rotated through the
3-D switch according to Figure 3(b) and is stored
in register block 1.
At the end of these operations, one phase of
the 3D-MDSA algorithm was executed and the
sorting process is continued in accordance with
27 phases.
One of the most important applications of the
proposed architecture is to find the largest/
smallest records in an array. This important
application is used in finding the operating task
with the shortest deadline time in real-time systems.19
It is necessary that the proposed architecture
finds one or more smallest tasks as soon
as possible with minimum amount of required
resources.
The ULP-Sorter can find and send four records
with the smallest value and four records with the
largest value to the output in its third sorting
phase. For this purpose, the host activates
" Mode " signal of ULP-Sorter. Then, the sorter can
be easily reconfigured to run in only three sorting
phases. In this case, the host receives only four
records with the smallest value and can replace it
with other records in the sorter.
IEEE Consumer Electronics Magazine - May/June 2022

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