IEEE Consumer Electronics Magazine - May/June 2022 - 92

Special Section on ISVLSI-2020
Table 1. Comparing ULP-Sorter With 3D-Sorter,17 Unary sort,10 RSN,18 H-Sort,15 and RTHS4.
The procedure of assigning input records in
each step is shown in Figure 5. In each step, the
input records are transferred from BRAMs to the
sorter unit. 2p sorted records are gained at the
end of step 2. More than 2p input records can be
sorted by the sorting package architecture.
EXPERIMENTAL RESULTS AND
ANALYSIS
In this article, we use a Spartan-7 FPGA
(XC7S75FGGA484, speed grade -2) to implement
ULP-Sorter. The Verilog HDL language based on
the RTHS open-source code20 is used to implement
ULP-Sorter. The Vivado-2018.2 software
tool is used for both synthesis and place-androute
procedures.
ULP-Sorter is compared with Unary sorter,10
RSN,18 H-Sort,15 3D-Sorter,17 and RTHS4 using the
following metrics: Resource utilization (number
of LUTs and CAS cells), design characteristics
(operating frequency), throughput, power consumption,
and efficiency (the achieved throughput
versus the power consumption).
The results are shown in Table 1. In total, 64
input records with w2-bit and 64-b data-width
are used for sorting in these experiments. The
techniques of ULP-Sorter, 3D-Sorter, and RTHS
are based on MDSA while the others sort an
array of one dimension with conventional sorting
algorithms.
Resource Utilization
The number of CAS cells is calculated based
on the equations presented by Norollah et al.4,17
Table 1 shows number of CAS cells for all
92
techniques except the RSN technique, as this
technique does not use a sorting network. The
number of CAS cells for ULP-Sorter when BSN is
used in the DBSN units is 24 cells. The number of
CAS cells for basic 3D-Sorter and RTHS is 96 and
192 cells, respectively. In fact, ULP-Sorter needs
4 and 8 lower CAS cells than the basic 3DSorter
and RTHS, respectively. However, it is
worth to note that OESN is used in the main
architecture of ULP-Sorter. The number of CAS
cells required by ULP-Sorter when utilizes OESN
in its DPSN structure is one-fourth of the number
of CAS cells required by the basic 3D-Sorter.
This article calculates the number of
required registers for each method based on the
equations presented by Norollah et al.4,17 A number
of required registers have been reported for
all techniques in Table 1. As can be seen, ULPSorter
decreases the number of required registers
on average by 60.7% and 31.25% in comparison
to RTHS and basic 3D-Sorter for both 32-b
and 64-b data-width, respectively. Moreover,
ULP-Sorter reduces the number of registers by
45.5% and 64.1% on average in comparison with
RSN and H-Sort, respectively. However, ULPSorter
needs 23% more required registers in
comparison with the unary sorter.10
According to Table 1, the number of LUTs has
been decreased by 68.5%, 75.6%, 81.5%, 60%, and
60.5% on average in comparison to RSN, H-Sort,
RTHS, unary sorter, and 3D-Sorter, respectively.
Design Characteristics
The operating frequency of RTHS, 3D-Sorter,
and RSN is 1.5, 1.25, and 1.18 on average
better than the operating frequency of ULPIEEE
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