IEEE Consumer Electronics Magazine - May/June 2022 - 93

CONCLUSIONS
This article introduces the ULP-Sorter that
Figure 6. Throughput to power consumption ratio.
(a) 32-b data width. (b) 64-b data width.
Sorter. However, ULP-Sorter has a better operating
frequency than H-Sort in the range of 1.3 on
average. The operating frequency of ULP-Sorter
and unary sorter is more and less the same.
Throughput Analysis
The throughput of RTHS, 3D-Sorter, and RSN
is 20,5, and 1.3 on average better than the
throughput of ULP-Sorter. However, the throughput
of ULP-Sorter is 4.3 on average better than
H-sort. As can be seen in Table 1, the throughput
of unary sorter is very low; hence, it is not comparable
with the throughput of ULP-Sorter.
Analysis of Power Consumption
The sum of both static and dynamic power
consumption is used to measure the power consumption
of an FPGA chip that includes the
power consumption of logic blocks, routing elements,
clock signals, and I/O. According to
Table 1, ULP-Sorter has decreased the power
consumption by 7.4%, 54.2%, 75.7%, 62.5%, and
34% for 32-b data-width and by 20.6%, 51%,
79.4%, 69.1%, and 33% for 64-b data-width, in
comparison to the Unary, RSN, H-Sort, RTHS,
and 3D-Sorter techniques, respectively.
Efficiency Measurement
Figure 6 illustrates the efficiency value [the
power consumption per throughput (GB/s)] for
the ULP-Sorter, and other state-of-the-art technique.
The maximum throughput with the least
power and resource consumption is the ultimate
goal of an ideal sorter that is a desirable design for
edge-computing devices. In the plot of throughput
versus power consumption, the bottom-right area
is the favorite area to achieve the best efficiency.
As can be seen, ULP-Sorter is the desired sorting
method for edge-computing devices.
May/June 2022
reduces number of required resources and power
consumption significantly in comparison with previous
state-of-the-art techniques. Although its
throughput and operating frequency have been
decreased in comparison with some previous
state-of-the-art techniques, it reduces number of
LUTs, required registers, and power consumption
significantly in comparison with previous state-ofthe-art
techniques. This issue motivates us to utilize
ULP-Sorter in edge-computing devices, where
we have serious limitation in the number of resources
andpower consumption.
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http://dx.doi.org/10.1109/MCE.2019.2923932 http://dx.doi.org/10.1007/s00778-011-0232-z http://dx.doi.org/10.1109/MCE.2018.2880807 http://dx.doi.org/10.1109/TVLSI.2019.2912554 http://dx.doi.org/10.1109/CODESS.2003.1275254 http://dx.doi.org/10.1109/CODESS.2003.1275254 http://dx.doi.org/10.1109/TCSVT.2004.828321 http://dx.doi.org/10.1109/TCSVT.2004.828321 http://dx.doi.org/10.1109/MCE.2020.2985656 http://dx.doi.org/10.1109/MCE.2020.2985656

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