IEEE Consumer Electronics Magazine - July/August 2022 - 61

Figure 3. (a) High level diagram of SMT architecture. (b) Example of two threads sharing a integer multiplier
unit. (c) If the spy process can access the integer multiplier unit the victim thread is not currently issuing a
multiply instruction. (d) If integer multiplier unit is already in use by the victim thread the spy thread will need to
wait to access it.
simulation was run to obtain base results.
Then, a fault list containing the location and
type of faults was provided to the simulator.
Each fault was simulated and the resulting
behavior was classified into one of the following
categories.
1) Silent data corruption: The execution completes
with incorrect results.
2) Time-out: The error slows down the GPU to
where it performs slower than the golden
GPU.
3) Hang: GPU cannot stop the execution.
4) Masked: The transient faults did not affect
the execution and the results of the simulation
are correct.
Architecture vulnerability factor was used to
evaluate fault simulator. It is computed across
all initial setups for each benchmark program by
taking the total number of failures that affected
the system over the total number of injections.
The authors concluded that increasing the number
of threads per block improved the mitigation
against SEUs when the registers were targeted.
However, the same was not true when other control
units were targeted (i.e., control units are
more vulnerable to faults).
SECURITY OF PARALLELISM
Parallel computing brings multiple resources
together to solve computationally hard problems.
With these new resources to be managed also
comes new bugs that may appear in a program.
For example, multiple processing units may want
to access shared memory, leading to contention.
Similarly, when an individual memory component
is updated in the case of distributed memory,
such an update must also be communicated
to the other units. Furthermore, interrupt handling
must also be managed across multiple
July/August 2022
processors. Such complexity in parallel computing
systems brings opportunities for bad actors to
take advantage of any foreseen weaknesses. In
many cases, detection becomes more difficult
since modern device details are kept hidden from
end-users. Sometimes, specific details of hardware
can be modified, or additional hardware
modules are added to provide defense against
possible exploits. Other times, defenses can be
incorporated into the software. However, many
of these defenses come at a cost. Once manufactured,
it is quite impossible to patch the
hardware. Even it becomes a possibility, new
hardware with security features may slow down
the program. Furthermore, software defenses
may increasememory usage or run time. In the following,
we present software- and hardware-based
attacks on parallel computing and possible
defenses.
Algorithm 1. Square and Multiply algorithm
implemented in OpenSSL
Data: Integers M and d, di is the ith bit of d
Result: MdðmodNÞ
S ¼ M;
for i to n 1do
S ¼ S SðmodNÞ;
if di ¼ 1 then
S ¼ SMðmodNÞ;
end
return S;
end
Software-based attacks: These attacks take
advantage of the execution model of a particular
victim program. A side-channel attack has been
performed on OpenSSL using simultaneous multithreading
(SMT).12 In general, SMT (also known
as HyperThreading in Intel processor) allows a
processor to issue multiple instructions from different
threads in the same instruction cycle.
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