IEEE Consumer Electronics Magazine - April 2017 - 119

architectural synthesis design of IP
chip sets protects lower-level designs
as the watermarking constraints traverse downward (in a top-down flow)
with synthesis. We demonstrate our
design approach by embedding a
watermark in the highest possible
abstraction level (during architectural
synthesis). Figure 2 shows the various
design phases of an antipiracy-aware IP
chip set. The details of RTL, gate-level, and layout synthesis are discussed
in [6] and [7].

Application, Library, Constraints
Resource Configuration

Scheduling

Select Desired Signature
Hardware Allocation and
Binding in Scheduled Graph
Decode Signature to
Convert to Watermarking
Constraints

SCHEDULING
Based on the application (specified
either as a control dataflow graph or
C-code), library, user design constraints,
and hardware resource constraints, the
scheduling of operations is performed
using the list scheduling algorithm. The
scheduled graph generated consists of
time stamps assigned to operations as
well as information on storage variables
(denoted by Vn). Data dependency is
taken into account while scheduling all
of the operations based on the resource
constraint specified.

HARDWARE ALLOCATION
AND BINDING
In this phase, hardware resources are
allocated to each operation, i.e., the
assignment of hardware units is made
for the scheduling operations. Allocation is followed by binding to determine the multiplexer and demultiplexer
information during resource sharing.
The respective hardware assignment is
indicated beside each operation in a
scheduled graph. Figure 3 shows such a
scheduled graph with the complete
hardware allocation (denoted by An or
Mn) and storage variable (denoted by
Vn) information for a MESA control
dataflow graph benchmark (used as an
IP chip set in multimedia and signal
processing applications of CE devices).
The benchmark is obtained from the
Express Benchmark Suite [8].

REGISTER ALLOCATION USING
COLORED INTERVAL GRAPHS
Register allocation is performed using a
colored interval graph, in which each
node represents a storage variable, and

Perform Register Allocation Using
Colored Interval Graph
Insert Constraints
into IP Design
Modified Register Allocation
Information in Scheduling

Watermarking

Multiplexing Scheme Based on
Modified Register Allocation
in Scheduling

Datapath

Controller

Architectural
Synthesis
Watermarked IP Core

RTL Synthesis

Gate-Level Synthesis

Watermarked IP Chip Set

Layout Synthesis

FIGURE 2. The proposed watermarked IP chip set design flow.

the edges between nodes indicate overlapping time steps between them. Having an edge between two nodes
suggests that a distinct register assignment is required between the storage

variables due to their overlapping time
steps (lifetimes). The colors of the interval graph indicate the minimum
number of registers required for assigning all of the storage variables without
april 2017

IEEE Consumer Electronics Magazine

119

Table of Contents for the Digital Edition of IEEE Consumer Electronics Magazine - April 2017