Table 3. A timing table for register allocation before embedding the watermark. Control Step Red Green Blue Yellow 0 V0 V1 V2 V3 1 V4 V5 V7 V6 2 V8 V9 V10 V6 3 V11 V12 - V13 4 V14 V12 - V15 5 V16 V12 - V15 6 V17 - - V15 Register 1 (R) * (M 1) (R) (A1) + (R) (M 1) * (R) + (A1) (R) V 16 (R) Register 2 V0 (R) V4 (G) (G) * V5 (M 2) (G) V8 (A2) Register 3 V1 * V 11 (M 2) (B) (Y) * (M 3) (A3) V 12 (Y) (M 3) + (A3) V7 + V 10 * + (A1) (M 4) * 1 V 13 V 15 DEMUX(1:4) 4 5 6 Register_P FIGURE 6. A scheduled and allocated graph of MESA with a watermark. R: red; G: green; B: blue; Y: yellow. Table 4. The multiplexing for the blue register containing the watermark. Table 5. The multiplexing for the blue register without the watermark. Time Input Output Time Input Output 0 Reg_I3 - 0 Reg_I3 - 1 M4_out M3_in 1 M3_out M3_in 2 A3_out A3_in 2 - M2_in 3 - M3_in 3 - 4 - - 4 - - 5 - - 5 - - 6 - - 6 - - 7 - - 7 - - april 2017 MUX(4:1) 3 V 17 ^ A3_out 2 Register_R 122 IEEE Consumer Electronics Magazine M4_out Reg_B (Y) V 14 * (B) V6 (M 4) V9 Reg_I3 V3 (B) + (G) Register 4 V 2 (Y) M3_in A3_in M3_in FIGURE 7. A pictorial representation of the portion of the datapath with a watermark in register B. Reg_I3 M3_out MUX(2:1) Reg_B DEMUX(1:2) M3_in M2_in FIGURE 8. A pictorial representation of the portion of the datapath without a watermark in register B.