IEEE Consumer Electronics Magazine - July 2015 - 61

Western Electronic Show and Convention in San Francisco.
That day, Ron Milner of Atari bought one to evaluate. On
the same day, Steve Wozniak of Apple bought one, which
ended up in the Apple I [14]. I also bought one and still
have it.
WHY DID tHIs CHangE tHE analYsIs? tHrEE rEasons
Cost
MOS technology was offering the part for US$25 for evaluation
samples and US$5 in large volume. That meant it was affordable.
semiConduCtor proCess
The 6502 used depletion-load n-type MOS (NMOS) on a single
+5-V power; many of the parts could handle 2-MHz memory.
In contrast, the MC6800 used enhancement-load MOS on a
single +5 dc supply; the average part could handle 500-kHz
memory. The Intel 8080 used enhancement-mode NMOS but
needed three dc power supplies: +12 V, +5 V, and -5 V; it could
handle 1-MHz memory. This made the 6502 fast enough from
a semiconductor process standpoint.
ArChiteCturAl speed
A lot of the computational load in embedded systems is in bit
manipulation, conditional branching, and building address
into tables of data. The 8080, a pioneering design, was slow
at it. A program has to build an address in the 8-bit H & L registers to form a 16-bit address before it can be used to move
data. (The latter Intel 8051 MPU was very good at bit manipulation [15].)

Bus Clock

The MC6800 was better at address generation, with a
16-bit index register offset by an immediate value, replacing
the H & L registers in the 8080. However, the 6800 was big
endian, which means that it took several clock cycles to do
the address arithmetic. A program branch, if taken or not,
took four memory clock cycles. In contrast, the 6502 was little
endian. A branch taken cost three memory cycles; a branch
not taken would cost only two memory cycles.
The 6502 family had several instruction modes designed to
accelerate dynamic address computation. First, they provided
for the first 256 locations (zero page) in external memory to
contain 16-bit memory addresses. Then, they defined two new
addressing modes to use those addresses: indexed indirect
addressing using the 8-bit X register, and indirect indexed
addressing using the 8-bit Y register.
In the first case, the second byte added to the X register
pointed to a 16-bit address in zero page memory. It would take
two cycles to load the opcode and offset, two more cycles to
load the 16-bit address, and that address was ready to use on
the fifth cycle (see Figure 2).
In the second case, the second byte pointed to a 16-bit memory address in zero page. That address would be added to the 8-bit
Y register to generate the final address. This took four cycles to
load the opcode, zero page offset, and 16-bit address; the computed resulting address was ready on the fifth cycle (see Figure 3).
The architectural speed made it possible to consider an
ASIC that supported a line buffer instead of an expensive

Address Bus

Data Bus

Description

Op Code

Load Instruction Using Indexed Indirect

PC + 1

ZPA Base Address 8-Bit Value Pointing to a Base Address in Zero Page

00:ZPA

Ignored

Dummy read

00:ZPA + X

DAL

Use X Register Offset to Choose a Pointer in Zero Page-
Fetch the Data Address Low Byte

00:ZPA + X + 1

DAH

Fetch the Data Address High Byte

DAH:DAL

-data-

Read or Write the Instruction Data

FIGURE 2. 6502 indexed indirect addressing using X register.

Bus Clock

Address Bus

Data Bus

Description

Op Code

Load Instruction Using Indexed Indirect

PC + 1

ZPA

8-Bit Value Pointing to a Base Address in Zero Page

00:ZPA

DAL

Fetch the Data Address Low Byte

00:ZPA + 1

DAH

Fetch the Data Address High Byte

DAH:DAL + Y

-data-

Add the Y Index Register to the DAL + DAH to Generate
the Instruction Address

FIGURE 3. 6502 indirect indexed addressing using Y register.

july 2015

IEEE Consumer Electronics Magazine

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