IEEE Consumer Electronics Magazine - July 2017 - 89

very-large-scale-integration community. Watermarking has
recently been extended to provide protection against false claims
of ownership and IP core piracy. Digital watermarking can be
embedded in different levels of hardware design abstraction
based on the designer's choice, where each level is imposing different tradeoff choices and design overhead [24], [25].
For the current generation of hardware design, multivendor IP core integration has become a mainstream practice as
it helps to achieve maximization of design productivity and
minimization of design time. An IP core is a piece of reusable
design with many man-years of investment. An IP core owner
is entitled to legal ownership rights, which must be protected
against false claims of ownership. Therefore, embedding a
digital watermark in the form of an encoded message (an
owner's sequence of digits) in the design is critical from the
vendor's perspective. Embedding a watermark in a hardware
design (regardless of the level of abstraction) must satisfy
several desirable properties [24], [25]:
▼ should not be detectable through a normal scan
▼ should not be easily reverse engineered by an adversary
who does not have full knowledge of the encoding rules
▼ should be fault tolerant, i.e., it should have the ability to
withstand minor tampering and indicate the rightful owner
▼ should yield minimal design overhead in terms of hardware area and delay
▼ should have zero tolerance for design or signal quality
degradation

should not even slightly alter the design functionality of
the IP core
▼ have low implementation complexity during embedding as
well as reverse engineering for a genuine user
▼ be robust against standard attacks
▼ be adaptable to suit modern CAD design tools.
A watermark for an IP core protection is performed by
embedding a vendor signature (in the form of encoded digits) in
any one or a combination of design steps. One of the specific
embodiments of watermarking is deployment for IP protection
by embedding a vendor signature during high-level synthesis
(i.e., at higher abstraction layers). The register allocation phase
during high-level synthesis is a step where the vendor signature
can be embedded as extra constraints such that storage variables
are forced to execute through distinct registers (based on the
encoding rule). However, it should not result in much storage
overhead and schedule delay. Multivariable-signature-encodingbased digital watermarking is considered more robust due to the
involvement of more than two encoding variables resulting in a
difficulty of reverse engineering by an adversary. Embedding
the watermark at a higher abstraction level provides flexibility
to choose an optimal design candidate solution (through design
space exploration), which minimizes the design overhead. Furthermore, the watermark may be embedded in register-transferlevel (RTL) designs in the form of dummy gates, blocks, and
more, without disturbing the functionality of the design and in
the FPGA-level designs in the form of bit streams. Moreover,
▼

Input
Video
Frames

Watermark Image
DCT

UNT

Frame Buffer

Controller
Watermark Embedding
Entropy
Coding

ZZ

Quantization

Entropy
Coding

ZZ

Quantization

Entropy
Coding

ZZ

Quantization

A

Watermark
Embedding IBP
Watermark Embedding I

ME

DCT

B

DCT
Quantization

C

ZZ Scanning
Drifting Watermark

Drift Compensation
IE

IZZ

IQuant

IDCT

MC

IE

IZZ

IQuant

IDCT

MC

IE

IZZ

IQuant

IDCT

MC

Datapath

C

Entropy Coding

-
+

B
A

+

-

Output Watermarked Stream

Control Signals

FIGURE 9. The system architecture of MPEG video watermarking on a compressed domain [20].

JULY 2017

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Table of Contents for the Digital Edition of IEEE Consumer Electronics Magazine - July 2017
