IEEE Solid-States Circuits Magazine - Spring 2018 - 20

Trimberger: Three Ages of FPGAs

and even automated placement and routing were not
considered essential. Many deemed it impractical even to
attempt design automation on the personal computers of
the time, since ASIC placement and routing was being
done on mainframe computers. Manual design, both
logical and physical, was acceptable because of the small
problem size. Manual design was often necessary because
of the limited routing resources on the chips [41].
Radically different architectures precluded universal
FPGA design tools, as were available in the ASIC business.
FPGA vendors took on the added burden of EDA development for their devices. This was eventually recognized
as an advantage, as FPGA vendors experimented and improved their architectures. The PAL vendors of the previous decade had relied upon external tool vendors to
provide software for mapping designs into their PALs. As a
result, PAL vendors were restricted to those architectures
the tool vendors supported, leading to commoditization,
low margins and lack of innovation. PLD architecture was
stifled while FPGA architecture flourished.
A further advantage of captive software development
was that FPGA customers were not required to purchase
tools from a third-party EDA company, which would have
increased their NRE costs. As they did with NRE charges,
FPGA vendors amortized their tool development costs into
their silicon pricing, keeping the up-front cost of using
their devices very low. EDA companies were not much
interested in FPGA tools anyway with their fragmented
market, low volume, low selling price, and requirement to
run on underpowered computers.
In the Age of Invention, FPGAs were much smaller than
the applications that users wanted to put into them. As a
result, multiple-FPGA systems [1], [42] became popular, and
automated multi-chip partitioning software was identified as
an important component of an FPGA design suite [36], even
as automatic placement and routing were not.

V. INTERL UDE: SHAKEOUT IN
FP GA B US I N E S S

Fig. 5. FPGA architecture genealogical tree, ca. 2000. All trademarks
are the property of their respective owners.

Pioneering the fabless business model, FPGA startup companies typically could not obtain leading-edge silicon technology in the early 1990s. As a result, FPGAs began the Age
of Expansion lagging the process introduction curve. In the
1990s, they became process leaders as the foundries realized
the value of using the FPGA as a process-driver application.
Foundries were able to build SRAM FPGAs as soon as they
were able to yield transistors and wires in a new technology.
FPGA vendors sold their huge devices while foundries
refined their processes. Each new generation of silicon
doubled the number of transistors available, which doubled
the size of the largest possible FPGA and halved the cost per
function. More import than simple transistor scaling, the
introduction of chemical-mechanical polishing (CMP)
permitted foundries to stack more metal layers. Valuable

The Age of Invention ended with brutal attrition in the FPGA
business. A modern reader may not recognize most of the
companies or product names in Section III and in the FPGA
genealogical tree in Fig. 5 [6], [38]. Many of the companies
simply vanished. Others quietly sold their assets as they
exited the FPGA business. The cause of this attrition was
more than the normal market dynamics. There were important changes in the technology, and those companies that did
not take advantage of the changes could not compete. Quantitative changes due to Moore's Law resulted in qualitative
changes in the FPGAs built with semiconductor technology.
These changes characterized the Age of Expansion.

VI . AGE OF E XP ANSION 1992-199 9
Through the 1990s, Moore's Law continued its rapid pace of
improvement, doubling transistor count every two years.
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Fig. 6. Growth of FPGA LUTs and interconnect wires Wire length is
measured in millions of transistor pitches.

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