IEEE Solid-States Circuits Magazine - Spring 2018 - 21

Trimberger: Three Ages of FPGAs

for ASICs, this capability was explosive for FPGAs because
the cost of valuable (nonbillable) interconnect dropped even
faster than the cost of transistors, and FPGA vendors
aggressively increased the interconnect on their devices to
accommodate the larger capacity (see Fig. 6).
This rapid process improvement had several effects
which we now examine.

A. Area Became Less Precious
No one who joined the FPGA industry in the mid-1990s
would agree that cost was unimportant or area was not
precious. However, those who had experienced the agonies of product development in the 1980s certainly saw the
difference. In the 1980s, transistor efficiency was necessary in order to deliver any product whatsoever. In the
1990s, it was merely a matter of product definition. Area
was still important, but now it could be traded off for
performance, features and ease-of-use. The resulting devices were less silicon efficient. This was unthinkable in
the Age of Invention just a few years earlier.
B. Design Automation Became Essential
In the Age of Expansion, FPGA device capacity increased rapidly as costs fell. FPGA applications became too
large for manual design. In 1992, the flagship Xilinx
XC4010 delivered a (claimed) maximum of 10 000 gates.
By 1999, the Virtex XCV1000 was rated at a million. In the
early 1990s, at the start of the Age of Expansion, automatic
placement and routing was preferred, but not entirely
trusted. By the end of the 1990s, automated synthesis [9],
placement and routing [3], [4], [19], [32], [37] were required
steps in the design process. Without the automation, the
design effort would be simply too great. The life of an FPGA
company was now dependent upon the ability of design
automation tools to target the device. Those FPGA companies that controlled their software controlled their future.
Cheaper metal from process scaling led to more programmable interconnect wire, so that automated placement
tools could succeed with a less-precise placement.
Automated design tools required automation-friendly
architectures, architectures with regular and plentiful
interconnect resources to simplify algorithmic decisionmaking. Cheaper wire also admitted longer wire segmentation, interconnect wires that spanned multiple logic
blocks [2], [28], [44]. Wires spanning many blocks effectively make physically distant logic logically closer, improving performance. The graph in Fig. 7 shows large
performance gains from a combination of process technology and interconnect reach. Process scaling alone would
have brought down the curve, but retained the shape;
longer segmentation flattened the curve. The longer segmented interconnect simplified placement because with
longer interconnect, it was not as essential to place two
blocks in exactly the right alignment needed to connect
them with a high performance path. The placer can do a
sloppier job and still achieve good results.

Fig. 7. Performance scaling with longer wire length segmentation.

On the down side, when the entire length of the wire
segment is not used, parts of the metal trace are effectively
wasted. Many silicon-efficient Age of Invention architectures were predicated on wiring efficiency, featuring short
wires that eliminated waste. Often, they rigidly followed
the two-dimensional limitation of the physical silicon giving those FPGAs the label ''cellular.'' In the Age of Expansion, longer wire segmentation was possible because the
cost of wasted metal was now acceptable. Architectures
dominated by nearest-neighbor-only connections could
not match the performance or ease-of-automation of architectures that took advantage of longer wire segmentation.
A similar efficiency shift applied to logic blocks. In the
Age of Invention, small, simple logic blocks were attractive
because their logic delay was short and because they
wasted little when unused or partially used. Half of the
configuration memory cells in a four-input LUT are wasted
when a three-input function is instantiated in it. Clever
designers could manually map complex logic structures
efficiently into a minimum number of fine-grained logic
blocks, but automated tools were not as successful. For
larger functions, the need to connect several small blocks
put greater demand on the interconnect. In the Age of
Expansion, not only were there more logic blocks, but the
blocks themselves became more complex.
Many Age of Invention architectures, built for efficiency with irregular logic blocks and sparse interconnect,
were difficult to place and route automatically. During the
Age of Invention, this was not a serious issue because the
devices were small enough that manual design was practical. But excessive area efficiency was fatal to many devices
and companies in the Age of Expansion. Fine-grained
architectures based on minimizing logic waste (such as the
Pilkington nand-gate block, the Algotronix/Xilinx 6200
Mux-based 2LUT block, the Crosspoint transistor-block)
simply died. Architectures that achieved their efficiency by
starving the interconnect also died. These included all
nearest-neighbor grid-based architectures. The Age of Expansion also doomed time-multiplexed devices [14], [39],
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