IEEE Solid-States Circuits Magazine - Spring 2018 - 26

Trimberger: Three Ages of FPGAs

Of course, this success led major FPGA manufacturers
to customize their FPGAs for the communications
industry. Made-for-communications FPGAs incorporated
high-speed I/O transceivers, thousands of dedicated highperformance multipliers, the ability to make wide data
paths and deep pipelines for switching large amounts of
data without sacrificing throughput. The dedicated blocks
and routing that were added to better serve the communications application requirements reduced the available
general logic area. By the end of the 2000s, FPGAs were
not general-purpose ASIC replacements as much as they
were data-routing engines. As multi-core processors and
general-purpose graphics processor units (GPGPUs) appeared, FPGAs were still preferred for high-throughput,
real-time computation. At the same time, FPGAs retained
their generality. FPGA bitwise programmability assured
their continued use in a wide range of applications, including control and automotive systems.

B. Moore's Law
Classical Dennard scaling, with simultaneous improvements in cost, capacity, power and performance, ended in
the mid-2000s [5], [18]. Subsequent technology generations still gave improvements in capacity and cost. Power
continued to improve also, but with a clear tradeoff against
performance. Performance gains from one technology node
to the next were modest and were traded off against power
savings. This effect is evident in the slowdown of performance growth in the 2000s in Fig. 1. These tradeoffs also
drove the accumulation of functions, because simple reliance on process technology scaling, as in the Age of
Expansion, was not sufficient to improve power and performance. Hardening the logic provided the needed
improvements.
We are now well into the next Age of FPGAs.
What is this next age?

XI II. CURRENT AGE: NO L ONGE R
PROGRAMMABLE LOGIC
By the end of the Age of Accumulation, FPGAs were not
arrays of gates, but collections of accumulated blocks integrated with the programmable logic. They were still
programmable but were not restricted to programmable
logic. The additional dimensions of programmability
acquired in the Age of Accumulation added design burden.
Design effort, an advantage for FPGAs in their competition
with ASIC, was a disadvantage in competition with newly
arrived multi-core processors and GPUs.
Pressures continued to mount on FPGA developers.
The economic slowdown beginning in 2008 continued to
drive the desire for lower cost. This pressure is exhibited
not only in the demand for lower price for functionality,
but also in lower power consumption, which reflects the
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Fig. 13. Estimated chip design cost, by process node, worldwide. Data:
Xilinx and Gartner. 2011.

cost of using the devices [29], [40]. Post-Dennard scaling
processing technology failed to deliver the huge concurrent benefits in cost, capacity, performance, power and
reliability that new process technology had delivered in
preceding decades. Of particular concern was the demand
for tradeoffs between power and performance. Now what?

A. Applications
During the Age of Accumulation, the ASIC companies
that brought custom devices to market in the 1980s were
quietly disappearing. Custom socket-specific ASIC devices
still existed, of course, but only for designs with very large
volume or extreme operating requirements. Did FPGAs
defeat them? Well, partially. In the 2000s, ASIC NRE
charges simply grew too large for most applications. This
can be seen in Fig. 13 where development cost in millions
of dollars is plotted against technology node. The development cost of a custom device reached tens, then hundreds of millions of dollars. A company that invests 20% of
income on research and development requires half a billion dollars revenue from sales of a chip to justify one
hundred million dollars development cost. The FPGA
crossover point reached millions of units. There are very
few chips that sell in that volume: notably microprocessors, memories and cell phone processors. Coupled with
tight financial controls in the wake of another recession,
the sales uncertainty and long lead time to revenue for new
products, the result was inescapable: if the application requirements could be met by a programmable device, programmable logic was the preferred solution. The FPGA
advantage from the very earliest days was still operating:
lower overall cost by sharing development cost.
ASICs did not die. ASICs survived and expanded by
adding programmability in the form of application specific
standard product (ASSP) system-on-chip (SoC) devices. An
SoC combines a collection of fixed function blocks along
with a microprocessor subsystem. The function blocks are

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2018